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| Da t a Sh e e t , DS 1 , M a rc h 2001 Q-SMINT(R)IX 2B1Q Second Gen. Modular ISDN NT (Intelligent eXtended) PEF 81912/81913 Version 1.3 Wi r ed Comm unic at ion s Never stop thinking. Edition March 2001 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany (c) Infineon Technologies AG 2001. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Da t a Sh e e t , DS 1 , M a rc h 2001 Q-SMINT(R)IX 2B1Q Second Gen. Modular ISDN NT (Intelligent eXtended) PEF 81912/81913 Version 1.3 Wi r ed Comm unic at ion s Never stop thinking. PEF 81912/81913 Revision History: Previous Version: Page All March 2001 Preliminary Data Sheet 10.00 DS 1 Subjects (major changes since last revision) Editorial changes, addition of notes for clarification etc. Table 1, Introduced new versions 81913 with extended performance of the U-interface Chapter 1.3 Chapter 2.1.1.1 Chapter 2.3.2 Figure 12 Chapter 2.5.5.2 Chapter 2.5.5.3 Chapter 2.6.2.1 Chapter 2.6.3.1 Chapter 4 SCI: header description: added to sequences 43H, 41H and 49H: ' Generally, it can be used for any register access to the address range 00H-7DH.' IOM-2 handler: removed 'U-transceiver (U)' from listing of functional units with programmable time slot and data port. Figure 'Data Access via CDAx0 and CDAx1 register pairs' corrected: input swap has influence on the input enable (EN_I0,1), too C/I commands: removed 'unconditional command' from description C/I-command 'DR' LT-S state machine: C/I=command AIL removed (no valid input to the LT-S state machine) HDLC: removed from description RBC: '(bytes, which are ready for next read access)' and '(blocks, which have been already read)'. HDLC: Possible Error Conditions: added behavioral description in case of an XPR interrupt Detailed register description: * U-transceiver Mode Evaluation Timing: clarified description * register ID: reset value of version 1.3 is 01H (not 00H) * RSTA.SA1,0: clarified note * CIX1.CODX1: bits 5-0 of C/I-channel 1 (not 7-2) * IOM_CR:TIC_DIS: added for clarification: 'This means that the timeslots TIC, A/ B, S/G and BAC are not available any more.' Chapter 5.1 Absolute Maximum Ratings: Maximum Voltage on VDD: 4.2V (before: 4.6V) Chapter 5.1 Refined references for ESD requirements:' ...(CDM), EIA/JESD22-A114B (HBM) ---' Chapter 5.2 Input/output leakage current set to 10A (before: 1A) Table 43 U-transceiver characteristics: enhanced S/N+D for 81913 and threshold level for 81912 and 81913 distinguished PEF 81912/81913 Revision History: Previous Version: Page Chapter 5.6.2 Chapter 5.6.3 Chapter 5.6.3 Chapter 5.6.5 March 2001 Preliminary Data Sheet 10.00 DS 1 Subjects (major changes since last revision) AC-Timing SCI/parallel C interface: enhanced timing specifications Added restriction for control interval tRI Parameters of the UVD/POR Circuit: defined reduced range of hysteresis: min. 30mV/max. 90mV relaxed upper limit of Detection Threshold to 2.92V (before: 2.9V) defined max. rising VDD for power-on Register summary U-transceiver 4B3T: Reset value of MASKU is FFH (not 00H) Chapter 7.2.5 Chapter 7.3 External circuitry for T-SMINT updated For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com PEF 81912/81913 Table of Contents 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.8.1 1.9 2 2.1 2.1.1 2.1.1.1 2.1.2 2.1.3 2.2 2.3 2.3.1 2.3.2 2.3.2.1 2.3.2.2 2.3.3 2.3.3.1 2.3.3.2 2.3.3.3 2.3.3.4 2.3.3.5 2.3.3.6 2.3.4 2.3.5 2.3.5.1 2.3.5.2 2.3.5.3 2.3.5.4 2.3.5.5 2.3.6 2.4 2.4.1 2.4.2 2.4.2.1 Page Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Features PEF 81912 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Features PEF 81913 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Not Supported are ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Different are ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Specific Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microcontroller Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Control Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microcontroller Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM(R)-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM(R)-2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM(R)-2 Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Controller Data Access (CDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Data Strobe Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM(R)-2 Monitor Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Handshake Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Treatment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MONITOR Channel Programming as a Master Device . . . . . . . . . . . MONITOR Channel Programming as a Slave Device . . . . . . . . . . . . Monitor Time-Out Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MONITOR Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C/I Channel Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-Channel Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Example for D-Channel Access Control . . . . . . . . . . . . . TIC Bus Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop/Go Bit Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-Channel Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . State Machine of the D-Channel Arbiter . . . . . . . . . . . . . . . . . . . . . . Activation/Deactivation of IOM(R)-2 Interface . . . . . . . . . . . . . . . . . . . . . U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2B1Q Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maintenance Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reporting to the C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 17 18 20 22 24 25 28 28 29 31 41 42 42 46 48 48 49 49 50 51 52 52 53 54 55 58 60 60 63 63 Data Sheet 2001-03-30 PEF 81912/81913 Table of Contents Page 2.4.2.2 Access from the C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.4.2.3 Availability of Maintenance Channel Information . . . . . . . . . . . . . . . . 64 2.4.2.4 M-Bit Register Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.4.3 Processing of the EOC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.4.3.1 EOC Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.4.3.2 EOC Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 2.4.3.3 EOC Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 2.4.3.4 Examples for different EOC modes . . . . . . . . . . . . . . . . . . . . . . . . . . 71 2.4.4 Processing of the Overhead Bits M4, M5, M6 . . . . . . . . . . . . . . . . . . . . 74 2.4.4.1 M4 Bit Reporting to the C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 2.4.4.2 M4 Bit Reporting to State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . 74 2.4.4.3 M5, M6 Bit Reporting to the C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 2.4.4.4 Summary of M4, M5, M6 Bit Reporting . . . . . . . . . . . . . . . . . . . . . . . 74 2.4.5 M4, M5, M6 Bit Control Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 2.4.6 Cyclic Redundancy Check / FEBE bit . . . . . . . . . . . . . . . . . . . . . . . . . . 78 2.4.7 Block Error Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 2.4.7.1 Near-End and Far-End Block Error Counter . . . . . . . . . . . . . . . . . . . 80 2.4.7.2 Testing Block Error Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 2.4.8 Scrambling/ Descrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 2.4.9 C/I Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 2.4.10 State Machines for Line Activation / Deactivation . . . . . . . . . . . . . . . . . 84 2.4.10.1 Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 2.4.10.2 Standard NT State Machine (IEC-Q / NTC-Q Compatible) . . . . . . . . 86 2.4.10.3 Inputs to the U-Transceiver: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 2.4.10.4 Outputs of the U-Transceiver: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 2.4.10.5 Description of the NT-States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 2.4.10.6 Simplified NT State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 2.4.11 Metallic Loop Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 2.4.12 U-Transceiver Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 2.5 S-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 2.5.1 Line Coding, Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 2.5.2 S/Q Channels, Multiframing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 2.5.3 Data Transfer between IOM-2 and S0 . . . . . . . . . . . . . . . . . . . . . . . . 105 2.5.4 Loopback 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 2.5.5 Control of S-Transceiver / State Machine . . . . . . . . . . . . . . . . . . . . . . 105 2.5.5.1 C/I Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 2.5.5.2 State Machine NT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 2.5.5.3 State Machine LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 2.5.6 S-Transceiver Enable / Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 2.5.7 Interrupt Structure S-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 2.6 HDLC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 2.6.1 Message Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Data Sheet 2001-03-30 PEF 81912/81913 Table of Contents 2.6.2 2.6.2.1 2.6.2.2 2.6.3 2.6.3.1 2.6.3.2 2.6.4 2.6.5 2.6.6 2.6.7 2.6.8 2.6.9 3 3.1 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.2 3.2.1 3.2.2 3.2.3 3.2.3.1 3.2.3.2 3.2.4 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 4 4.1 4.2 4.3 4.4 4.5 4.6 4.6.1 Page 120 120 126 128 128 133 134 134 135 136 137 138 139 139 139 140 141 142 143 144 144 145 146 146 147 147 149 149 149 151 153 154 155 155 156 158 Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Structure and Control of the Receive FIFO . . . . . . . . . . . . . . . . . . . Receive Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Structure and Control of the Transmit FIFO . . . . . . . . . . . . . . . . . . Transmit Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Access to IOM(R)-2 channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extended Transparent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HDLC Controller Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Layer 1 Activation/Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Complete Activation Initiated by Exchange . . . . . . . . . . . . . . . . . . . . . Complete Activation Initiated by TE . . . . . . . . . . . . . . . . . . . . . . . . . . . Complete Activation Initiated by NT . . . . . . . . . . . . . . . . . . . . . . . . . . . Complete Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loop 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Layer 1 Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Loopback U-Transceiver (No. 3) . . . . . . . . . . . . . . . . . . . . . . . Analog Loop-Back S-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loopback No.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Complete Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loopback No.2 - Single Channel Loopbacks . . . . . . . . . . . . . . . . . . Local Loopbacks Featured By the LOOP Register . . . . . . . . . . . . . . . External Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Blocking Recommendation . . . . . . . . . . . . . . . . . . . . . . U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset of U-Transceiver Functions During Deactivation or with C/I-Code RESET 166 U-Transceiver Mode Register Evaluation Timing . . . . . . . . . . . . . . . . . . Detailed HDLC Control and C/I Registers . . . . . . . . . . . . . . . . . . . . . . . . RFIFO - Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 168 168 Data Sheet 2001-03-30 PEF 81912/81913 Table of Contents 4.6.2 4.6.3 4.6.4 4.6.5 4.6.6 4.6.7 4.6.8 4.6.9 4.6.10 4.6.11 4.6.12 4.6.13 4.6.14 4.6.15 4.6.16 4.6.17 4.6.18 4.6.19 4.6.20 4.6.21 4.7 4.7.1 4.7.2 4.7.3 4.7.4 4.7.5 4.7.6 4.7.7 4.7.8 4.7.9 4.8 4.8.1 4.8.2 4.8.3 4.8.4 4.8.5 4.8.6 4.9 4.9.1 4.9.2 4.9.3 4.9.4 Data Sheet Page 168 169 171 171 172 174 175 177 177 178 179 179 180 180 181 183 183 184 185 186 186 186 188 188 189 190 191 191 192 193 194 194 195 196 197 198 199 199 199 200 201 202 XFIFO - Transmit FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISTAH - Interrupt Status Register HDLC . . . . . . . . . . . . . . . . . . . . . . . MASKH - Mask Register HDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STAR - Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CMDR - Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MODEH - Mode Register HDLC Controller . . . . . . . . . . . . . . . . . . . . . EXMR - Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIMR - Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAP1 - SAPI1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAP2 - SAPI2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RBCL - Receive Frame Byte Count Low . . . . . . . . . . . . . . . . . . . . . . . RBCH - Receive Frame Byte Count High for D-Channel . . . . . . . . . . TEI1 - TEI1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEI2 - TEI2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RSTA - Receive Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMH -Test Mode Register HDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CIR0 - Command/Indication Receive 0 . . . . . . . . . . . . . . . . . . . . . . . . CIX0 - Command/Indication Transmit 0 . . . . . . . . . . . . . . . . . . . . . . . . CIR1 - Command/Indication Receive 1 . . . . . . . . . . . . . . . . . . . . . . . . CIX1 - Command/Indication Transmit 1 . . . . . . . . . . . . . . . . . . . . . . . . Detailed S-Transceiver Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S_CONF0 - S-Transceiver Configuration Register 0 . . . . . . . . . . . . . . S_CONF2 - S-Transmitter Configuration Register 2 . . . . . . . . . . . . . . S_STA - S-Transceiver Status Register . . . . . . . . . . . . . . . . . . . . . . . S_CMD - S-Transceiver Command Register . . . . . . . . . . . . . . . . . . . . SQRR - S/Q-Channel Receive Register . . . . . . . . . . . . . . . . . . . . . . . SQXR- S/Q-Channel Transmit Register . . . . . . . . . . . . . . . . . . . . . . . ISTAS - Interrupt Status Register S-Transceiver . . . . . . . . . . . . . . . . . MASKS - Mask S-Transceiver Interrupt . . . . . . . . . . . . . . . . . . . . . . . . S_MODE - S-Transceiver Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt and General Configuration Registers . . . . . . . . . . . . . . . . . . . . ISTA - Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MASK - Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MODE1 - Mode1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MODE2 - Mode2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID - Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRES - Software Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed IOM(R)-2 Handler Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CDAxy - Controller Data Access Register xy . . . . . . . . . . . . . . . . . . . . XXX_TSDPxy - Time Slot and Data Port Selection for CHxy . . . . . . . CDAx_CR - Control Register Controller Data Access CH1x . . . . . . . . S_CR - Control Register S-Transceiver Data . . . . . . . . . . . . . . . . . . . 2001-03-30 PEF 81912/81913 Table of Contents 4.9.5 4.9.6 4.9.7 4.9.8 4.9.9 4.9.10 4.9.11 4.9.12 4.9.13 4.10 4.10.1 4.10.2 4.10.3 4.10.4 4.10.5 4.10.6 4.11 4.11.1 4.11.2 4.11.3 4.11.4 4.11.5 4.11.6 4.11.7 4.11.8 4.11.9 4.11.10 4.11.11 4.11.12 4.11.13 4.11.14 4.11.15 4.11.16 4.11.17 4.11.18 4.11.19 5 5.1 5.2 5.3 5.4 5.5 Page 204 205 206 207 208 209 209 210 210 211 211 211 212 212 213 214 214 214 215 216 217 218 218 219 220 221 222 222 223 223 224 225 226 226 227 228 229 229 230 232 232 232 HCI_CR - Control Register for HDLC and CI1 Data . . . . . . . . . . . . . . MON_CR - Control Register Monitor Data . . . . . . . . . . . . . . . . . . . . . SDS1_CR - Control Register Serial Data Strobe 1 . . . . . . . . . . . . . . . SDS2_CR - Control Register Serial Data Strobe 2 . . . . . . . . . . . . . . . IOM_CR - Control Register IOM Data . . . . . . . . . . . . . . . . . . . . . . . . . MCDA - Monitoring CDA Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STI - Synchronous Transfer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . ASTI - Acknowledge Synchronous Transfer Interrupt . . . . . . . . . . . . . MSTI - Mask Synchronous Transfer Interrupt . . . . . . . . . . . . . . . . . . . Detailed MONITOR Handler Registers . . . . . . . . . . . . . . . . . . . . . . . . . . MOR - MONITOR Receive Channel . . . . . . . . . . . . . . . . . . . . . . . . . . MOX - MONITOR Transmit Channel . . . . . . . . . . . . . . . . . . . . . . . . . . MOSR - MONITOR Interrupt Status Register . . . . . . . . . . . . . . . . . . . MOCR - MONITOR Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . MSTA - MONITOR Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . MCONF - MONITOR Configuration Register . . . . . . . . . . . . . . . . . . . . Detailed U-Transceiver Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OPMODE - Operation Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . MFILT - M Bit Filter Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EOCR - EOC Read Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EOCW - EOC Write Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M4RMASK - M4 Read Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . M4WMASK - M4 Write Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . M4R - M4 Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M4W - M4 Write Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M56R - M56 Read Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M56W - M56 Write Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UCIR - C/I Code Read Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UCIW - C/I Code Write Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEST - Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LOOP - Loop Back Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FEBE - Far End Block Error Counter Register . . . . . . . . . . . . . . . . . . NEBE - Near End Block Error Counter Register . . . . . . . . . . . . . . . . . ISTAU - Interrupt Status Register U-Interface . . . . . . . . . . . . . . . . . . . MASKU - Mask Register U-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . FW_VERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet 2001-03-30 PEF 81912/81913 Table of Contents 5.6 5.6.1 5.6.2 5.6.3 5.6.4 5.6.5 6 7 7.1 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.3 8 Page 233 234 236 237 240 241 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM(R)-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial P Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel P Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Undervoltage Detection Characteristics . . . . . . . . . . . . . . . . . . . . . . . Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Appendix: Differences between Q- and T-SMINTIX . . . . . . . . . . . . . . Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . U-Interface Conformity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . U-Transceiver State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command/Indication Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 245 246 246 247 250 251 253 256 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 Data Sheet 2001-03-30 PEF 81912/81913 List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Data Sheet Page Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Application Example Q-SMINT(R)IX: Low Cost Intelligent NT . . . . . . . . 14 Control via P Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Control via IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Serial Control Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Serial Command Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Direct/Indirect Register Address Mode . . . . . . . . . . . . . . . . . . . . . . . . 24 Reset Generation of the Q-SMINT(R)IX . . . . . . . . . . . . . . . . . . . . . . . . . 25 IOM(R)-2 Frame Structure of the Q-SMINT(R)IX . . . . . . . . . . . . . . . . . . . 28 Architecture of the IOM(R)-2 Handler. . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Data Access via CDAx0 and CDAx1 register pairs . . . . . . . . . . . . . . . 32 Examples for Data Access via CDAxy Registers . . . . . . . . . . . . . . . . . 33 Data Access when Looping TSa from DU to DD . . . . . . . . . . . . . . . . . 34 Data Access when Shifting TSa to TSb on DU (DD) . . . . . . . . . . . . . . 35 Example for Monitoring Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Interrupt Structure of the Synchronous Data Transfer . . . . . . . . . . . . . 39 Examples for the Synchronous Transfer Interrupt Control with one STIxy enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Data Strobe Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 MONITOR Channel Protocol (IOM(R)-2) . . . . . . . . . . . . . . . . . . . . . . . . 44 Monitor Channel, Transmission Abort requested by the Receiver. . . . 47 Monitor Channel, Transmission Abort requested by the Transmitter. . 47 Monitor Channel, Normal End of Transmission . . . . . . . . . . . . . . . . . . 47 MONITOR Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 CIC Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 D-Channel Arbitration: C has no HDLC and no Direct Access to TIC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Structure of Last Octet of Ch2 on DU . . . . . . . . . . . . . . . . . . . . . . . . . 53 Structure of Last Octet of Ch2 on DD . . . . . . . . . . . . . . . . . . . . . . . . . 54 State Machine of the D-Channel Arbiter (Simplified View). . . . . . . . . . 56 Deactivation of the IOM(R)-2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 U-Superframe Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 U-Basic Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 U2B1Q Framer - Data Flow Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . 62 U2B1Q Deframer - Data Flow Scheme . . . . . . . . . . . . . . . . . . . . . . . . 63 Write Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Read Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 EOC Message Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 EOC Command/Message Transmission . . . . . . . . . . . . . . . . . . . . . . . 69 Maintenance Channel Filtering Options . . . . . . . . . . . . . . . . . . . . . . . . 75 M4 Bit Report Timing (Statemachine vs. C). . . . . . . . . . . . . . . . . . . . 75 2001-03-30 PEF 81912/81913 List of Figures Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55 Figure 56 Figure 57 Figure 58 Figure 59 Figure 60 Figure 61 Figure 62 Figure 63 Figure 64 Figure 65 Figure 66 Figure 67 Figure 68 Figure 69 Figure 70 Figure 71 Figure 72 Figure 73 Figure 74 Figure 75 Figure 76 Figure 77 Figure 78 Figure 79 Figure 80 Figure 81 Data Sheet Page M4, M5, M6 Bit Control in Receive Direction . . . . . . . . . . . . . . . . . . . . 77 M4, M5, M6 Bit Control in Transmit Direction . . . . . . . . . . . . . . . . . . . 77 CRC-Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Block Error Counter Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Explanation of State Diagram Notation . . . . . . . . . . . . . . . . . . . . . . . . 84 Standard NT State Machine (IEC-Q / NTC-Q Compatible) (Footnotes: see "Dependence of Outputs" on Page 91) . . . . . . . . . 86 Simplified NT State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Pulse Streams Selecting Quiet Mode . . . . . . . . . . . . . . . . . . . . . . . . . 99 Interrupt Structure U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 S/T -Interface Line Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Frame Structure at Reference Points S and T (ITU I.430). . . . . . . . . 103 S-Transceiver Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 State Diagram Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 State Machine NT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 State Machine LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Interrupt Structure S-Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 RFIFO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Data Reception Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Reception Sequence Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Receive Data Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Data Transmission Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Transmission Sequence Example . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Transmit Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Interrupt Status Registers of the HDLC Controller . . . . . . . . . . . . . . . 137 Layer 2 Test Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Complete Activation Initiated by Exchange . . . . . . . . . . . . . . . . . . . . 139 Complete Activation Initiated by TE . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Complete Activation Initiated by Q-SMINT(R)IX. . . . . . . . . . . . . . . . . . 141 Complete Deactivation Initiated by Exchange . . . . . . . . . . . . . . . . . . 142 Loop 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Test Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 External Loop at the S/T-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Complete Loopback Options in NT-Mode . . . . . . . . . . . . . . . . . . . . . 146 Loopbacks Featured by Register LOOP . . . . . . . . . . . . . . . . . . . . . . 148 Power Supply Blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 External Circuitry U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 External Circuitry S-Interface Transmitter . . . . . . . . . . . . . . . . . . . . . 152 External Circuitry S-Interface Receiver . . . . . . . . . . . . . . . . . . . . . . . 153 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Address Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 2001-03-30 PEF 81912/81913 List of Figures Figure 82 Figure 83 Figure 84 Figure 85 Figure 86 Figure 87 Figure 88 Figure 89 Figure 90 Figure 91 Figure 92 Figure 93 Figure 94 Figure 95 Figure 96 Figure 97 Figure 98 Figure 99 Figure 100 Figure 101 Figure 102 Page 156 233 233 234 234 236 237 237 237 238 238 238 239 240 241 247 248 249 251 252 256 Q-SMINT(R)IX Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . Maximum Sinusoidal Ripple on Supply Voltage . . . . . . . . . . . . . . . Input/Output Waveform for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . IOM(R)-2 Interface - Bit Synchronization Timing . . . . . . . . . . . . . . . . . IOM(R)-2 Interface - Frame Synchronization Timing . . . . . . . . . . . . . . Serial Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microprocessor Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microprocessor Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microprocessor Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microprocessor Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Undervoltage Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INTC-Q Compatible State Machine Q-SMINT(R)IX: 2B1Q . . . . . . . . . Simplified State Machine Q-SMINT(R)IX: 2B1Q . . . . . . . . . . . . . . . . . IEC-T/NTC-T Compatible State Machine T-SMINTIX: 4B3T . . . . . . Interrupt Structure U-Transceiver Q-SMINT(R)IX: 2B1Q . . . . . . . . . . . Interrupt Structure U-Transceiver T-SMINTIX: 4B3T . . . . . . . . . . . . External Circuitry Q- and T-SMINTIX . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet 2001-03-30 PEF 81912/81913 List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Page NT Products of the 2nd Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 HDLC Naming Convention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ACT States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Interface Selection for the Q-SMINT(R)IX . . . . . . . . . . . . . . . . . . . . . . . 17 Header Byte Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Bus Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 MCLK Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Reset Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Examples for Synchronous Transfer Interrupts . . . . . . . . . . . . . . . . . . 38 Transmit Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Receive Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Q-SMINT(R)IX Configuration Settings in Intelligent NT Applications . . . 55 Major Differences D-Channel Arbiter INTC-Q and Q-SMINT(R)IX. . . . . 56 U-Superframe Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Enabling the Maintenance Channel (Receive Direction) . . . . . . . . . . . 64 Coding of EOC-Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Usage of Supported EOC-Commands. . . . . . . . . . . . . . . . . . . . . . . . . 67 EOC Auto Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Transparent mode 6 ms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Transparent mode '@change' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Transparent mode TLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 U - Transceiver C/I Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Timers Used. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 U-Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Signal Output on Uk0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 C/I-Code Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Changes to achieve Simplified NT State Machine . . . . . . . . . . . . . . . . 95 Appearance of the State Machine to the Software . . . . . . . . . . . . . . . 98 ANSI Maintenance Controller States . . . . . . . . . . . . . . . . . . . . . . . . . . 99 S/Q-Bit Position Identification and Multi-Frame Structure . . . . . . . . . 104 Receive Byte Count with RBC11...0 in the RBCH and RBCL registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Receive Information at RME Interrupt . . . . . . . . . . . . . . . . . . . . . . . . 128 XPR Interrupt (availability of the XFIFO) after XTF, XME Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 U-Transformer Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 S-Transformer Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Crystal Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Reset of U-Transceiver Functions During Deactivation or with C/I-Code RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 2001-03-30 Data Sheet PEF 81912/81913 List of Tables Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Table 50 Page 229 230 231 232 240 241 245 246 250 257 Maximum Input Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S-Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . U-Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Input Signal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . Parameters of the UVD/POR Circuit . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Related Documents to the U-Interface. . . . . . . . . . . . . . . . . . . . . . . . C/I Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dimensions of External Components. . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet 2001-03-30 PEF 81912/81913 Overview 1 Overview The PEF 81912 / 81913 (Q-SMINT(R)IX) offers most features known from the PEB / PEF 8191 [12] and can hence replace the latter in its major applications. However, it does not replace the PEB/PEF 8191 in applications that use the S-transceiver in TE mode. The Q-SMINT(R)IX features U-transceiver, S-transceiver, HDLC controller and an IOM(R)2 interface on a single chip. A microcontroller interface provides access to both transceivers, the HDLC controller as well as the IOM(R)-2 interface. Main target applications of the Q-SMINT(R)IX are intelligent NT applications which require one single HDLC controller. Table 1 summarizes the 2nd generation NT products. * Table 1 NT Products of the 2nd Generation PEF80912 PEF80913 PEF81912 PEF81913 PEF82912 PEF82913 Q-SMINT(R)O Q-SMINT(R)IX P-MQFP-64 P-TQFP-64 U+S+HDLC+ IOM(R)-2 parallel (or SCI or IOM(R)-2) yes Q-SMINT(R)I P-MQFP-64 P-TQFP-64 U+S+ IOM(R)-2 parallel (or SCI or IOM(R)-2) yes Package Register access Access via MCLK, watchdog timer, SDS, BCL, Dchannel arbitration, IOM(R)-2 access and manipulation etc. provided HDLC controller NT1 mode available Extended UPerformance 20kft Data Sheet P-MQFP-44 no n.a. no no yes (only) no yes no yes no yes no no no yes 1 2001-03-30 PEF 81912/81913 Overview 1.1 [1] [2] References TS 102 080, Transmission and Multiplexing ; ISDN basic rate access; Digital transmission system on metallic local lines, ETSI, November 1998 T1.601-1998 (Revision of ANSI T1.601-1992), ISDN-Basic Access Interface for Use on Metallic Loops for Application on the Network Side of the NT (Layer 1 Specification), ANSI, 1998 ST/LAA/ELR/DNP/822, CNET, France RC7355E, 2B1Q Generic Physical Layer Specification, British Telecommunications plc., 1997 FZA TS 0095/01:1997-10, Technische Spezifikationen fur Netzabschlugerate fur den ISDN Basisanschlu (NT-BA), Post & Telekom Austria, 1997 pr ETS 300 012 Draft, ISDN; Basic User Network Interface (UNI), ETSI, November 1996 T1.605-1991, ISDN-Basic Access Interface for S and T Reference Points (Layer 1 Specification), ANSI, 1991 I.430, ISDN User-Network Interfaces: Layer 1 Recommendations, ITU, November 1988 IEC-Q, ISDN Echocancellation Circuit, PEB 2091 V4.3, User's Manual 02.95, Siemens AG, 1995 SBCX, S/T Bus Interface Circuit Extended, PEB 2081 V3.4, User's Manual 11.96, Siemens AG, 1996 NTC-Q, Network Termination Controller (2B1Q), PEB / PEF 8091 V1.1, Data Sheet 10.97, Siemens AG, 1997 INTC-Q, Intelligent Network Termination Controller (2B1Q), PEB / PEF 8191 V1.1, Data Sheet 10.97, Siemens AG, 1997 IOM(R)-2 Interface Reference Guide, Siemens AG, 03.91 SCOUT-S(X), Siemens Codec with S/T-Transceiver, PSB 2138x V1.3, Preliminary Data Sheet 8.99, Infineon Technologies, 1999 PITA, PCI Interface for Telephony/Data Applications V0.3, SICAN GmbH, September 1997 Dual Channel SLICOFI-2, HV-SLIC; DUSLIC; PEB3265, 4265, 4266; Data Sheet DS2, Infineon Technologies, July 2000. [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] * Data Sheet 2 2001-03-30 PEF 81912/81913 Overview * 2B1Q Second Gen. Modular ISDN NT (Intelligent eXtended) Q-SMINT(R)IX Version 1.3 PEF 81912/81913 1.2 Features PEF 81912 Features known from the PEB/PEF 8191 * U-transceiver, S-transceiver and HDLC controller on one chip * Perfectly suited for low-cost intelligent NTs that P-MQFP-64-1,-2 require one single HDLC controller * U-interface (2B1Q) conform to ETSI [1], ANSI [2] and P-MQFP-64 CNET [3]: - Meets all transmission requirements on all ETSI, ANSI and CNET loops with margin - Conform to British Telecom's RC7355E [4] - Compliant with ETSI 10 ms micro interruptions - MLT input and decode logic (ANSI [2]) * S/T-interface conform to ETSI [6], ANSI [7] and ITU P-TQFP-64-1 [8] - Supports point-to-point and bus configurations P-TQFP-64 - Meets and exceeds all transmission requirements * Activation status LED supported * BCL, SDS1, SDS2, programmable MCLK, watchdog timer, * Access to IOM(R)-2 C/I and Monitor channels * Power-down mode and reset states (e.g. S-transceiver) for individual circuits * Automatic D-channel arbitration between S-bus and local HDLC controller * Parallel or serial P-interface Type PEF 81912/81913 PEF 81912/81913 Data Sheet 3 Package P-MQFP-64 P-TQFP-64 2001-03-30 PEF 81912/81913 Overview * New Features * * * * * * * * * * * * * * * * * * * * * Reduced number of external components for external U-hybrid required Optional use of up to 2x20 resistors on the line side of the transformer (e.g. PTCs) Pin Uref and the according external capacitor removed Improved ESD (2 kV instead of <850 V) Inputs accept 3.3 V and 5 V I/O (open drain) accepts pull-up to 3.3 V1) LED signal is programmable but can also automatically indicate the activation status (mode select via 1 bit) Pin compatible with T-SMINT(R)IX (2nd Generation) Priority setting (8/10) for off-chip and on-chip HDLC controller Improved FIFO structure (SCOUT) Enhanced IOM(R)-2 timeslot access and manipulation (SCOUT) HDLC extended transparent mode (SCOUT) MCLK can be disabled (SCOUT) External Awake (EAW) Optional: All registers can be read and written to via new Monitor channel concept Optional: Implementation of S-transceiver statemachine in software Indirect Addressing (SCOUT) HDLC access to B-channels, D-channel and any combination of them Programmable strobes SDS1/2 are more flexible, e.g. active during several timeslots Power-on reset and Undervoltage Detection with no external components Lowest power consumption due to: - Low power CMOS technology (0.35) - Newly optimized low-power libraries - High output swing on U- and S-line interface leads to minimized power consumption - Single 3.3 Volt power supply 200 mW (INTC-Q: 295 mW) power consumption with random data over ETSI Loop 2 (external loads on the S and U interface only and no additional external loads). 15 mW typical power consumption in power down (INTC-Q: 28 mW) * * 1.3 Features PEF 81913 The Q-SMINT(R)IX PEF 81913 provides all features of the PEF 81912. Additionally, a significantly enhanced performance of the U-interface as compared to ETSI [1], ANSI [2] and CNET [3] requirements is guaranteed: Transparent transmission on 20kft AWG26 with a BER < 10-7 (without noise). 1) Pull-ups to 5 V must be avoided. A so-called 'hot-electron-effect' would lead to long term degradation. Data Sheet 4 2001-03-30 PEF 81912/81913 Overview 1.4 * * * * * * * * Not Supported are ... Integrated U-hybrid 'Self test request' and 'Self test passed' of U-transceiver TE-mode of the S-transceiver DECT-link capability SRA (capacitive receiver coupling is not suited for S-feeding). 'NT-Star' with star point on the IOM(R)-2 bus (already not supported in INTC-Q). HDLC Automode No access to S2-5 channels. Access only to S1 and Q channel as in SCOUT. No selection between transparent and non-auto mode provided. * The oscillator architecture was changed with respect to the INTC-Q to reduce power consumption. As a consequence, the Q-SMINT(R)IX always needs a crystal and pin XIN can not be connected to an external clock as it was possible for IEC-Q and NTCQ. This does not limit the use of the Q-SMINT(R)IX in NTs since all NT designs use crystals anyway. 1.5 Different are ... * HDLC naming convention of transparent modes has changed (as in SCOUT). The according bit combination in the MODEH register remains unchanged, hence software compatibility is ensured. Table 2 HDLC Naming Convention New Transparent 2 Transparent 0 Transparent 1 Address comparison TEI none SAPI Old (ICC/INTC-Q) Transparent 1 Transparent 2 Transparent 3 Data Sheet 5 2001-03-30 PEF 81912/81913 Overview 1.6 * Pin Configuration /VDDDET TP2 VDDa_SR VSSa_SR A5 A6 PS1 49 50 51 52 53 54 55 56 57 SR2 SR1 VDDa_SX VSSa_SX SX2 SX1 TP1 PS2 A4 A3 A2 A1 A0 BCL DU DD 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Q-SMINT IX PEF 81912/ PEF 81913 (R) XOUT XIN BOUT VDDa_UX VSSa_UX AOUT 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 FSC DCL VSSD VDDD AD7 or SDX AD6 or SDR AD5 or SCLK AD4 AD3 AD2 AD1 AD0 /EAW MCLK /ACT pin_2.vsd Figure 1 Pin Configuration Data Sheet SDS1 ALE /WR or R/W /RD or /DS /CS VDDD VSSD /INT MTI 6 VSSa_UR VDDa_UR AIN BIN /RST /RSTO SDS2 2001-03-30 PEF 81912/81913 Overview 1.7 * Block Diagram XIN SR1 XOUT VDDDET RST RSTO PS1 PS2 MTI Clock Generation SR2 POR/UVD AOUT BOUT SX1 SX2 S-Transceiver U-Tansceiver D-Channel Arbitration AIN BIN to P IF TP1 TP2 Factory Tests HDLC Controller FIFO to P IF M O N C/I TIC C D A W D T LED ACT IOM-2 Interface P Interface (e.g. Multiplexed Mode) FSC DCL BCL DU DD SDS1 SDS2 AD0-AD7 ALE RD WR CS INT MCLK EAW block diagram.vsd Figure 2 Block Diagram Data Sheet 7 2001-03-30 PEF 81912/81913 Overview 1.8 * Pin Definitions and Functions Pin Definitions and Functions Pin 2 1 62 63 51 52 46 45 29 30 13 14 32 31 Symbol VDDa_UR Table 3 Type - - - - - - - - - - - - O O Function Supply voltage for U-Receiver (3.3 V 5 %) Analog ground (0 V) U-Receiver Supply voltage for U-Transmitter (3.3 V 5 %) Analog ground (0 V) U-Transmitter Supply voltage for S-Receiver (3.3 V 5 %) Analog ground (0 V) S-Receiver Supply voltage for S-Transmitter (3.3 V 5 %) Analog ground (0 V) S-Transmitter Supply voltage digital circuits (3.3 V 5 %) Ground (0 V) digital circuits Supply voltage digital circuits (3.3 V 5 %) Ground (0 V) digital circuits Frame Sync: 8-kHz frame synchronization signal Data Clock: IOM(R)-2 interface clock signal (double clock): 1.536 MHz Bit Clock: The bit clock is identical to the IOM(R)-2 data rate (768 kHz) Data Downstream: Data on the IOM(R)-2 interface Data Upstream: Data on the IOM(R)-2 interface VSSa_UR VDDa_UX VSSa_UX VDDa_SR VSSa_SR VDDa_SX VSSa_SX VDDD VSSD VDDD VSSD FSC DCL 35 BCL O 33 34 DD DU I/O OD I/O OD Data Sheet 8 2001-03-30 PEF 81912/81913 Overview Table 3 8 Pin Definitions and Functions (cont'd) Pin Symbol SDS1 Type O Function Serial Data Strobe1: Programmable strobe signal for time slot and/ or D-channel indication on IOM(R)-2 Serial Data Strobe2: Programmable strobe signal for time slot and/ or D-channel indication on IOM(R)-2 Chip Select: A low level indicates a microcontroller access to the Q-SMINT(R)IX Serial Clock: Clock signal of the SCI interface if a serial interface is selected Multiplexed Bus Mode: Address/data bus Address/data line AD5 if the parallel interface is selected Non-Multiplexed Bus Mode: Data bus Data line D5 if the parallel interface is selected Serial Data Receive: Receive data line of the SCI interface if a serial interface is selected Multiplexed Bus Mode: Address/data bus Address/data line AD6 if the parallel interface is selected Non-Multiplexed Bus Mode: Data bus Data line D6 if the parallel interface is selected 7 SDS2 O 12 CS I 26 SCLK I 26 AD5 I/O 27 SDR I 27 AD6 I/O Data Sheet 9 2001-03-30 PEF 81912/81913 Overview Table 3 Pin Definitions and Functions (cont'd) Pin 28 Symbol SDX Type OD,O Function Serial Data Transmit: Transmit data line of the SCI interface if a serial interface is selected Multiplexed Bus Mode: Address/data bus Address/data line AD7 if the parallel interface is selected Non-Multiplexed Bus Mode: Data bus Data line D7 if the parallel interface is selected Multiplexed Bus Mode: Address/data bus Transfers addresses from the microcontroller to the Q-SMINT(R)IX and data between the microcontroller and the Q-SMINT(R)IX. Non-Multiplexed Bus Mode: Data bus. Transfers data between the microcontroller and the Q-SMINT(R)IX (data lines D0-D4). Non-Multiplexed Bus Mode: Address bus transfers addresses from the microcontroller to the Q-SMINT(R)IX. For indirect address mode only A0 is valid. Multiplexed Bus Mode Not used in multiplexed bus mode. In this case A0-A6 should directly be connected to VDD. Read Indicates a read access to the registers (Intel bus mode). Data Strobe The rising edge marks the end of a valid read or write operation (Motorola bus mode). 28 AD7 I/O 21 22 23 24 25 AD0 AD1 AD2 AD3 AD4 I/O I/O I/O I/O I/O 36 37 38 39 40 53 54 11 A0 A1 A2 A3 A4 A5 A6 RD I I I I I I I I DS I Data Sheet 10 2001-03-30 PEF 81912/81913 Overview Table 3 Pin Definitions and Functions (cont'd) Pin 10 Symbol WR Type I Function Write Indicates a write access to the registers (Intel bus mode). Read/Write A HIGH identifies a valid host access as a read operation and a LOW identifies a valid host access as a write operation (Motorola bus mode). Address Latch Enable An address on the external address/data bus (multiplexed bus type only) is latched with the falling edge of ALE. ALE also selects the microcontroller interface type (multiplexed or non multiplexed). Reset: Low active reset input. Schmitt-Trigger input with hysteresis of typical 360 mV. Tie to '1' if not used. Reset Output: Low active reset output. Interrupt Request: INT becomes active if the Q-SMINT(R)IX requests an interrupt. Microcontroller Clock: Clock output for the microcontroller Tie to `1` EAW I External Awake: A low level on EAW during power down activates the clock generation of the QSMINT(R)IX, i.e. the IOM(R)-2 interface provides FSC, DCL and BCL for read and write access.1) S-Bus Transmitter Output (positive) S-Bus Transmitter Output (negative) S-Bus Receiver Input R/W I 9 ALE I 5 RST I 6 15 RSTO INT OD OD 18 19 20 MCLK O 43 44 47 SX1 SX2 SR1 O O I Data Sheet 11 2001-03-30 PEF 81912/81913 Overview Table 3 Pin Definitions and Functions (cont'd) Pin 48 60 59 Symbol SR2 XIN XOUT Type I I O Function S-Bus Receiver Input Crystal 1: Connected to a 15.36 MHz crystal Crystal 2: Connected to a 15.36 MHz crystal Differential U-interface Output Differential U-interface Output Differential U-interface Input Differential U-interface Input VDD Detection: This pin selects if the VDD detection is active ('0') and reset pulses are generated on pin RSTO or whether it is deactivated ('1') and an external reset has to be applied on pin RST. Metallic Termination Input. Input to evaluate Metallic Termination pulses. Tie to '1' if not used. Power Status (primary). The pin status is passed to the overhead bit 'PS1' in the U frame to indicate the status of the primary power supply ('1' = ok). Power Status (secondary). The pin status is passed to the overhead bit 'PS2' in the U frame to indicate the status of the secondary power supply ('1' = ok). Activation LED. Indicates the activation status of U- and Stransceiver. Can directly drive a LED (4 mA). Test Pin 1. Used for factory device test. Tie to VSS 64 61 3 4 49 AOUT BOUT AIN BIN VDDDET O O I I I 16 MTI I 55 PS1 I 41 PS2 I 17 ACT O 42 TP1 I Data Sheet 12 2001-03-30 PEF 81912/81913 Overview Table 3 Pin Definitions and Functions (cont'd) Pin 50 Symbol TP2 Type I Function Test Pin 2. Used for factory device test. Tie to VSS Reserved 56, 57, 58 1) res This function of pin EAW is different to that defined in Ref. [14] I: Input O: Output (Push-Pull) OD: Output (Open Drain) 1.8.1 Specific Pins LED Pin ACT A LED can be connected to pin ACT to display four different states (off, slow flashing, fast flashing, on). It displays the activation status of the U- and S-transceiver according to Table 4. or it is programmable via two bits (LED1 and LED2 in register MODE2). Table 4 Pin ACT VDD 8Hz 1Hz GND with: U_Deactivated: 'Deactivated State' as defined in Chapter 2.4.10.5. If the `Simplified State Machine` is selected: 'Deactivated State' and `IOM(R)-2 Awaked`. U_Activated: 'Synchronized 1', 'Synchronized 2', 'Wait for ACT', 'Transparent', 'Error S/ T', 'Pend. Deact. S/T', 'Pend. Deact. U' as defined in Chapter 2.4.10.5. S-Activated: 'Activated State' as defined in Chapter 2.5.5. ACT States LED off 8Hz 1Hz on U_Deactivated 1 0 0 0 U_Activated x 0 1 1 S_Activated x x 0 1 Note: Optionally, pin ACT can drive a second LED with inverse polarity (connect this additional LED to 3.3 V only). Data Sheet 13 2001-03-30 PEF 81912/81913 Overview Test Modes The test patterns on the S-interface (`2 kHz Single Pulses`, `96 kHz Continuous Pulses`) and on the U-interface (`Data Through`, `Send Single Pulses`) are invoked via C/I codes (TM1, TM2, DT, SSP). Setting SRES.RES_U to `1` forces the U-transceiver into test mode `Quiet Mode` (QM), i.e. the U-transceiver is hardware reset. 1.9 * System Integration DC/DC-Converter IDCC PEB2023 MLT S/T - Interface S Q-SMINTIX PEF 81912 PEF 81913 U - Interface U HDLC / FIFO POTS Interface P HV - SLIC SLICOFI-2 HV - SLIC IOM-2 C513 LCNTappl.vsd Figure 3 Application Example Q-SMINT(R)IX: Low Cost Intelligent NT The U-transceiver, S-transceiver, the IOM(R)-2 channels and the HDLC-controller can be controlled and monitored via: a) the parallel or serial microprocessor interface - Access of on-chip registers via P interface Address/Data format - Activation/Deactivation control of U- and S-transceiver via P interface and C/I handler - Q-SMINT(R)IX is Monitor channel master - TIC bus is transparent on IOM(R)-2-interface and is used for D-channel arbitration between S-transceiver, on-chip and off-chip HDLC controllers. Data Sheet 14 2001-03-30 PEF 81912/81913 Overview * S C/I0 C/I1 U MON Mon C/I Register IOM -2 c - Interface IOM-2 Slave e.g. SLICOFI-2 c iommaster.vsd Figure 4 Control via P Interface Alternatively, the Q-SMINT(R)IX can be controlled via b) the IOM(R)-2 Interface - Access of on-chip registers via the Monitor channel with Header/Address/Data format (Device is Monitor slave) - Activation/Deactivation control of U- and S-transceiver via the C/I channels CI0 and CI1 - TIC bus is transparent on IOM(R)-2-interface and is used for D-channel arbitration between S-transceiver, on-chip and off-chip HDLC controllers. Data Sheet 15 2001-03-30 PEF 81912/81913 Overview * S C/I1 C/I0 U MON Register IOM -2 INT IOM-2 Master e.g. UTAH iomslave.vsd Figure 5 Control via IOM(R)-2 Interface Data Sheet 16 2001-03-30 PEF 81912/81913 Functional Description 2 2.1 Functional Description Microcontroller Interfaces The Q-SMINT(R)IX supports either a serial or a parallel microcontroller interface. For applications where no controller is connected to the Q-SMINT(R)IX microcontroller interface, register programming is done via the IOM(R)-2 MONITOR channel from a master device. In such applications the Q-SMINT(R)IX operates in the IOM(R)-2 slave mode (refer to the corresponding chapter of the IOM(R)-2 MONITOR handler). The interface selections are all done by pinstrapping. The possible interface selections are listed in Table 5. The selection pins are evaluated when the reset input RST is released. For the pin levels stated in the tables the following is defined: 'High':dynamic pin value which must be 'High' when the pin level is evaluated VDD, VSS:static 'High' or 'Low' level (tied to VDD, VSS) * Table 5 PINS WR (R/W) RD (DS) Interface Selection for the Q-SMINT(R)IX Serial /Parallel Interface PINS CS ALE VDD Interface Type/Mode Motorola Siemens/Intel Non-Mux Siemens/Intel Mux Serial Control Interface(SCI) IOM(R)-2 MONITOR Channel (Slave Mode) 'High' 'High' VSS VSS Parallel Serial `High' 'High' VSS VSS edge VSS VSS Note: For a selected interface mode which does not require all pins (e.g. address pins) the unused pins must be tied to VDD. The microcontroller interface also consists of a microcontroller clock generation at pin MCLK, an interrupt request at pin INT, a reset input pin RST and a reset output pin RSTO. The interrupt request pin INT (open drain output) becomes active if the Q-SMINT(R)IX requests an interrupt. Data Sheet 17 2001-03-30 PEF 81912/81913 Functional Description 2.1.1 Serial Control Interface (SCI) The serial control interface (SCI) is compatible to the SPI interface of Motorola and to the Siemens C510 family of microcontrollers. The SCI consists of 4 lines: SCLK, SDX, SDR and CS. Data is transferred via the lines SDR and SDX at the rate given by SCLK. The falling edge of CS indicates the beginning of a serial access to the registers. The Q-SMINT(R)IX latches incoming data at the rising edge of SCLK and shifts out at the falling edge of SCLK. Each access must be terminated by a rising edge of CS. Data is transferred in groups of 8 bits with the MSB first. Pad mode of SDX can be selected 'open drain' or 'push-pull' by programming MODE2.PPSDX. Figure 6 shows the timing of a one byte read/write access via the serial control interface. Data Sheet 18 2001-03-30 PEF 81912/81913 Functional Description * Write Access CS SCLK Header Command/Address Data SDR 765432107654321076543210 0 write SDX Read Access CS SCLK Header Command/Address SDR 7654321076543210 1 read Data SDX 76543210 SCI_TIM.VSD Figure 6 Data Sheet Serial Control Interface Timing 19 2001-03-30 PEF 81912/81913 Functional Description 2.1.1.1 Programming Sequences The basic structure of a read/write access to the Q-SMINT(R)IX registers via the serial control interface is shown in Figure 7. * write sequence: write byte 2 byte 3 header SDR 7 0 address (command) 07 write data 0 07 6 read sequence: read byte 2 header SDR 7 1 address (command) 07 byte 3 07 6 0 SDX read data Figure 7 Serial Command Structure A new programming sequence starts with the transfer of a header byte. The header byte specifies different programming sequences allowing a flexible and optimized access to the individual functional blocks of the Q-SMINT(R)IX. The possible sequences are listed in Table 6 and are described after that. * Table 6 Header Byte 40H 48H 43H 41H 49H Header Byte Code Sequence Adr-Data-Adr-Data Adr-Data-Data-Data Sequence Type non-interleaved interleaved Read-/Write-only non-interleaved interleaved Address Range 00H-7FH Access to Address Range 00H-7FH Data Sheet 20 2001-03-30 PEF 81912/81913 Functional Description Header 40H: Non-interleaved A-D-A-D Sequences The non-interleaved A-D-A-D sequences give direct read/write access to the address range 00H-7FH and can have any length. In this mode SDX and SDR can be connected together allowing data transmission on one line. Example for a read/write access with header 40H: SDR SDX header wradr wrdata rdadr rddata rdadr rddata wradr wrdata Header 48H: Interleaved A-D-A-D Sequences The interleaved A-D-A-D sequences give direct read/write access to the address range 00H-7FH and can have any length. This mode allows a time optimized access to the registers by interleaving the data on SDX and SDR. Example for a read/write access with header 48H: SDR SDX header wradr wrdata rdadr rdadr rddata wradr rddata wrdata Header 43H: Read-/Write- only A-D-D-D Sequence This mode (header 43H) can be used for a fast access to the HDLC FIFO data. Any address (rdadr, wradr) in the range between 00H-1FH gives access to the current FIFO location selected by an internal pointer which is automatically incremented with every data byte following the first address byte. Generally, it can be used for any register access to the address range 00H-7DH. The sequence can have any length and is terminated by the rising edge of CS. Example for a write access with header 43H: SDR SDX Example for a read access with header 43H: SDR SDX header rdadr rddata (rdadr) header wradr wrdata (wradr) wrdata (wradr) wrdata (wradr) wrdata (wradr) wrdata (wradr) wrdata (wradr) wrdata (wradr) rddata (rdadr) rddata (rdadr) rddata (rdadr) rddata (rdadr) rddata (rdadr) rddata (rdadr) Data Sheet 21 2001-03-30 PEF 81912/81913 Functional Description Header 41H: Non-interleaved A-D-D-D Sequence This sequence (header 41H) allows in front of the A-D-D-D write access a noninterleaved A-D-A-D read access. This mode is useful for reading status information before writing to the HDLC XFIFO. Generally, it can be used for any register access to the address range 00H-7DH. The termination condition of the read access is the reception of the wradr. The sequence can have any length and is terminated by the rising edge of CS. Example for a read/write access with header 41H: SDR SDX header rdadr rddata rdadr rddata wradr wrdata (wradr) wrdata (wradr) wrdata (wradr) Header 49H: Interleaved A-D-D-D Sequence This sequence (header 49H) allows in front of the A-D-D-D write access an interleaved A-D-A-D read access. This mode is useful for reading status information before writing to the HDLC XFIFO. Generally, it can be used for any register access to the address range 00H-7DH. The termination condition of the read access is the reception of the wradr. The sequence can have any length and is terminated by the rising edge of CS. Example for a read/write access with header 49H: SDR SDX header rdadr rdadr rddata wradr rddata wrdata (wradr) wrdata (wradr) wrdata (wradr) 2.1.2 Parallel Microcontroller Interface The 8-bit parallel microcontroller interface with address decoding on chip allows an easy and fast microcontroller access. The parallel interface of the Q-SMINT(R)IX provides three types of P busses which are selected via pin ALE. The bus operation modes with corresponding control pins are listed in Table 7. * Table 7 Bus Operation Modes Pin ALE VDD VSS Edge Control Pins CS, R/W, DS CS, WR, RD CS, WR, RD, ALE Bus Mode (1) Motorola (2) Siemens/Intel non-multiplexed (3) Siemens/Intel multiplexed Data Sheet 22 2001-03-30 PEF 81912/81913 Functional Description The occurrence of an edge on ALE, either positive or negative, at any time during the operation immediately selects the interface type (3). A return to one of the other interface types is possible only if a hardware reset is issued. Note: For a selected interface mode which does not require all pins (e.g. address pins) the unused pins must be tied to VDD. A read/write access to the Q-SMINT(R)IX registers can be done in multiplexed or nonmultiplexed mode. In non-multiplexed mode the register address must be applied to the address bus (A0A6) for the data access via the data bus (D0-D7). In multiplexed mode the address on the address bus (AD0-AD7) is latched in by ALE before a read/write access via the address/data bus is performed. The Q-SMINT(R)IX provides two different ways to address the register contents which can be selected with the AMOD bit in the MODE2 register. The address mode after reset is the indirect address mode (AMOD = '0'). Reprogramming into the direct address mode (AMOD = '1') has to take place in the indirect address mode. Figure 8 illustrates both register addressing modes. Direct address mode (AMOD = '1'): The register address to be read or written is directly set in the way described above. Indirect address mode (AMOD = '0'): * non-muxed: only the LSB of the address bus (A0) * muxed: only the LSB of the address-data bus (AD0) gets evaluated to address a virtual ADDRESS (0H) and a virtual DATA (1H) register. Every access to a target register consists of: * a write access (muxed or non-muxed) to ADDRESS to store the target registers address, as well as * a read access (muxed or non-muxed) from DATA to read from the target register or * a write access (muxed or non-muxed) to DATA to write to the target register Data Sheet 23 2001-03-30 PEF 81912/81913 Functional Description * Direct Address Mode AMOD = 1 D7 - D0 A6 - A0 7Fh 7Eh 7Dh 7Ch Data A0 Indirect Address Mode AMOD = 0 (default) D7 - D0 Data 04h 03h 02h 01h 00h 1h 0h DATA ADDRESS regacces.vsd Figure 8 Direct/Indirect Register Address Mode 2.1.3 Microcontroller Clock Generation The microcontroller clock is derived from the unregulated 15.36 MHz clock from the oscillator and provided by the pin MCLK. Five clock rates are selectable by a programmable prescaler which is controlled by the bits MODE1.MCLK and MODE1.CDS corresponding to the following table. Table 8 MODE1. MCLK Bits 0 0 1 1 0 1 0 1 MCLK Frequencies MCLK frequency with MODE1.CDS = '0' 3.84 MHz 0.96 MHz 7.68 MHz disabled MCLK frequency with MODE1.CDS = '1' 7.68 MHz 1.92 MHz 15.36 MHz disabled The clock rate is changed after CS becomes inactive. Data Sheet 24 2001-03-30 PEF 81912/81913 Functional Description 2.2 *. Reset Generation Figure 9 shows the organization of the reset generation of the Q-SMINT(R)IX. RSS1 C/I0 Code Change (Exchange Awake) 125s t 250s 0 1,x 1 0,0 RSTO 1 RSS2,1 0,1= open t = 125s RSS2,1 Watchdog Deactivation Delay Software Reset Register (SRES) Reset MODE1 Register 1 0 VDDDET RES_CI Reset Functional Block POR/UVD RES_HDLC RES_S 0 RES_U 1 VDDDET 1 Internal Reset of all Registers RST Pin RESETGEN.VSD Figure 9 Reset Generation of the Q-SMINT(R)IX1) Reset Source Selection The internal reset sources C/I code change and Watchdog timer can be output at the low active reset pin RSTO. These reset sources can be selected with the RSS2,1 bits in the MODE1 register according to Table 9. 1) The 'OR'-gates shall illustrate in a symbolic way, that 'source A active' or 'source B active' is forwarded. The real polarity of the different sources is not considered. Data Sheet 25 2001-03-30 PEF 81912/81913 Functional Description The internal reset sources set the MODE1 register to its reset value. Table 9 RSS2 Bit 1 0 0 1 1 1) Reset Source Selection RSS1 Bit 0 0 1 0 1 x -C/I Code Change -Watchdog Timer -/RSTO disabled (= high impedance) -x x x POR/UVD1) and RST x POR/UVD can be enabled/disabled via pin VDDDET * * C/I Code Change (Exchange Awake) A change in the downstream C/I channel (C/I0) generates a reset pulse of 125 s t 250 s. * Watchdog Timer After the selection of the watchdog timer (RSS = '11') an internal timer is reset and started. During every time period of 128 ms the microcontroller has to program the WTC1- and WTC2 bits in the following sequence to reset and restart the watchdog timer: WTC1 1. 2. 1 0 WTC2 0 1 Otherwise the timer expires and a WOV-interrupt (ISTA Register) together with a reset out pulse on pin RSTO of 125 s is generated. Deactivation of the watchdog timer is only possible with a hardware reset (including expiration of the watchdog timer). As in the SCOUT-S, the watchdog timer is clocked with the IOM(R)-2 clocks and works only if the internal IOM(R)-2 clocks are active. Hence, the power consumption is minimized in state power down. Software Reset Register (SRES) Several main functional blocks of the Q-SMINT(R)IX can be reset separately by software setting the corresponding bit in the SRES register. This is equivalent to a hardware reset of the corresponding functional block. The reset state is activated as long as the bit is set to '1'. Data Sheet 26 2001-03-30 PEF 81912/81913 Functional Description External Reset Input At the RST input an external reset can be applied forcing the Q-SMINT(R)IX in the reset state. This external reset signal is additionally fed to the RSTO output. After release of an external reset, the C has to wait for min. tC before it starts read or write access to the Q-SMINT(R)IX (see Table 45). Reset Ouput If VDDDET is active, then the deactivation of a reset output on RSTO is delayed by tDEACT (see Table 46). Reset Generation The Q-SMINT(R)IX has an on-chip reset generator based on a Power-On Reset (POR) and Under Voltage Detection (UVD) circuit (see Table 46). The POR/UVD requires no external components. The POR/UVD circuit can be disabled via pin VDDDET. The requirements on VDD ramp-up during power-on reset are described in Chapter 5.6.5. Clocks and Data Lines During Reset During reset the data clock (DCL), the bit clock (BCL), the microcontroller clock1) (MCLK) and the frame synchronization (FSC) keep running. During reset DD and DU are high; with the exception of: * The output C/I code from the U-Transceiver on DD IOM(R)-2 channel 0 is 'DR' = 0000 (Value after reset of register UCIR = '00H') * The output C/I code from the S-Transceiver on DU IOM(R)-2 channel 1 is 'TIM' = 0000. 1) during a Power-On/UVD Reset, the microcontroller clock MCLK is not running, but starts running as soon as timer tDEAC is started. Data Sheet 27 2001-03-30 PEF 81912/81913 Functional Description 2.3 IOM(R)-2 Interface The Q-SMINT(R)IX supports the IOM(R)-2 interface in terminal mode (DCL=1.536 MHz) according to the IOM(R)-2 Reference Guide [13]. 2.3.1 IOM(R)-2 Functional Description The IOM(R)-2 interface consists of four lines: FSC, DCL, DD, DU and optionally BCL. The rising edge of FSC indicates the start of an IOM(R)-2 frame. The DCL and the BCL clock signals synchronize the data transfer on both data lines DU and DD. The DCL is twice the bit rate, the BCL rate is equal to the bit rate. The bits are shifted out with the rising edge of the first DCL clock cycle and sampled at the falling edge of the second clock cycle. With BCL the bits are shifted out with the rising edge and sampled with the falling edge of the single clock cycle. The IOM(R)-2 interface can be enabled/disabled with the DIS_IOM bit in the IOM_CR register. The FSC signal is an 8 kHz frame sync signal. The number of PCM timeslots on the receive and transmit lines is determined by the frequency of the DCL clock (or BCL), with the 1.536 MHz (BCL=768 kHz) clock 3 channels consisting of 4 timeslots each are available. IOM(R)-2 Frame Structure of the Q-SMINT(R)IX The frame structure on the IOM(R)-2 data ports (DU,DD) of the Q-SMINT(R)IX with a DCL clock of 1.536 MHz (or BCL=768 kHz) and if TIC bus is not disabled (IOM_CR.TIC_DIS) is shown in Figure 10. * macro_19 Figure 10 IOM(R)-2 Frame Structure of the Q-SMINT(R)IX Data Sheet 28 2001-03-30 PEF 81912/81913 Functional Description The frame is composed of three channels * Channel 0 contains 144-kbit/s of user and signaling data (2B + D), a MONITOR programming channel (MON0) and a command/indication channel (CI0) for control and programming of e.g. the U-transceiver. * Channel 1 contains two 64-kbit/s intercommunication channels (IC), a MONITOR programming channel (MON1) and a command/indication channel (CI1) for control and programming of e.g. the S-transceiver. * Channel 2 is used for D-channel access mechanism (TlC-bus, S/G bit). Additionally, channel 2 supports further IC and MON channels. 2.3.2 IOM(R)-2 Handler The IOM(R)-2 handler offers a great flexibility for handling the data transfer between the different functional units of the Q-SMINT(R)IX and voice/data devices connected to the IOM(R)-2 interface. Additionally it provides a microcontroller access to all time slots of the IOM(R)-2 interface via the four controller data access registers (CDA). The PCM data of the functional units * S-transceiver (S) and the * Controller data access (CDA) can be configured by programming the time slot and data port selection registers (TSDP). With the TSS bits (Time Slot Selection) the PCM data of the functional units can be assigned to each of the 12 PCM time slots of the IOM(R)-2 frame. With the DPS bit (Data Port Selection) the output of each functional unit is assigned to DU or DD respectively. The input is assigned vice versa. With the control registers (CR) the access to the data of the functional units can be controlled by setting the corresponding control bits (EN, SWAP). The IOM(R)-2 handler also provides access to the * * * * * U and S transceiver MONITOR channel C/I channels (CI0,CI1) TIC bus (TIC) and D- and/or B-channel for HDLC control The access to these channels is controlled by the registers S_CR, HCI_CR and MON_CR. The IOM(R)-2 interface with the two Serial Data Strobes (SDS1,2) is controlled by the control registers IOM_CR, SDS1_CR and SDS2_CR. The following Figure 11 shows the architecture of the IOM(R)-2 handler. Data Sheet 29 2001-03-30 PEF 81912/81913 Functional Description BCL/SCLK SDS1 IOM-2 Handler SDS1/2_CR IOM_CR IOM-2 Interface (EN, OD) (EN, TLEN, TSS) TIC Bus Data SDS2 FSC DCL DU DD D/B1/B2 Data C/I0 Data Monitor Data Controller Data Access (CDA) Architecture of the IOM(R)-2 Handler CDA Data C/I0 Data C/I1 Data D Data CDA Registers CDA10 CDA11 CDA20 CDA21 (TSDP, DPS, EN, SWAP, TBM, MCDA, STI) CDA_TSDPxy CDA_CRx MCDA STI MSTI ASTI Control Data Access Control Monitor Data TIC Bus Disable Control C/I1 Data Control HDLC B1-Data EN B2-Data EN D-Data EN MON_CR IOM_CR HCI_CR Control Transceiver Data Access (TSS, DPS, EN) Transceiver Data (TR=U/S) S_TSDP_B1 S_TSDP_B2 S_CR TR_B1_X TR_B2_X TR_D_X TR_B1_R TR_B2_R TR_D_R TR represents the U and S transceiver MON Handler TIC C/I0 Data C/I1 B1/B2/D-ch FIFOs 21150_0 7 Microcontroller Interface Data Sheet * Figure 11 30 2001-03-30 PEF 81912/81913 Functional Description 2.3.2.1 Controller Data Access (CDA) The four controller data access registers (CDA10, CDA11, CDA20, CDA21) provide microcontroller access to the 12 IOM(R)-2 time slots and more: * looping of up to four independent PCM channels from DU to DD or vice versa over the four CDA registers * shifting or switching of two independent PCM channels to another two independent PCM channels on both data ports (DU, DD). Between reading and writing the data can be manipulated (processed with an algorithm) by the microcontroller. If this is not the case a switching function is performed. * monitoring of up to four time slots on the IOM(R)-2 interface simultaneously * microcontroller read and write access to each PCM channel The access principle, which is identical for the two channel register pairs CDA10/11 and CDA20/21, is illustrated in Figure 12. The index variables x,y used in the following description can be 1 or 2 for x, and 0 or 1 for y. The prefix 'CDA_' from the register names has been omitted for simplification. To each of the four CDAxy data registers a TSDPxy register is assigned by which the time slot and the data port can be determined. With the TSS (Time Slot Selection) bits a time slot from 0...11 can be selected. With the DPS (Data Port Selection) bit the output of the CDAxy register can be assigned to DU or DD respectively. The time slot and data port for the output of CDAxy is always defined by its own TSDPxy register. The input of CDAxy depends on the SWAP bit in the control registers CRx. If the SWAP bit = '0' (swap is disabled) the time slot and data port for the input and output of the CDAxy register is defined by its own TSDPxy register. If the SWAP bit = '1' (swap is enabled) the input port and time slot of the CDAx0 is defined by the TSDP register of CDAx1 and the input port and time slot of CDAx1 is defined by the TSDP register of CDAx0. The input definition for time slot and data port CDAx0 are thus swapped to CDAx1 and for CDAx1 swapped to CDAx0. The output timeslots are not affected by SWAP. The input and output of every CDAxy register can be enabled or disabled by setting the corresponding EN (-able) bit in the control register CDAx_CR. If the input of a register is disabled the output value in the register is retained. Usually one input and one output of a functional unit (transceiver, HDLC controller, CDA register) is programmed to a timeslot on IOM(R)-2 (e.g. for B-channel transmission in upstream direction the S-transceiver writes data onto IOM(R)-2 and the U-transceiver reads data from IOM(R)-2). For monitoring data in such cases a CDA register is programmed as described below under "Monitoring Data". Besides that none of the IOM(R)-2 timeslots must be assigned more than one input and output of any functional unit. Data Sheet 31 2001-03-30 PEF 81912/81913 Functional Description *. TSa Control Register CDA_CRx 1 0 TSb DU 0 1 Time Slot Selection (TSS) Enable output (EN_O0) input (EN_I0) 1 Input Swap (SWAP) 1 input (EN_I1) Enable output (EN_O1) CDA_TSDPx0 Time Slot Selection (TSS) 1 1 CDAx0 1 1 CDAx1 Data Port Selection (DPS) 0 1 1 0 TSa x = 1 or 2; a,b = 0...11 TSb IOM_HAND.FM4 Figure 12 Data Access via CDAx0 and CDAx1 register pairs Looping and Shifting Data Figure 13 gives examples for typical configurations with the above explained control and configuration possibilities with the bits TSS, DPS, EN and SWAP in the registers TSDPxy or CDAx_CR: a) looping IOM(R)-2 time slot data from DU to DD or vice versa (SWAP = '0') b) shifting data from TSa to TSb and TSc to TSd in both transmission directions (SWAP = '1') c) switching data from TSa to TSb and looping from DU to DD or switching TSc to TSd and looping from DD to DU . TSa is programmed in TSDP10, TSb in TSDP11, TSc in TSDP20 and TSd in TSDP21. Data Sheet 32 2001-03-30 Data Port Selection (DPS) DD CDA_TSDPx1 PEF 81912/81913 Functional Description * a) Looping Data TSa TSb TSc TSd DU CDA10 CDA11 CDA20 CDA21 .TSS: TSa TSb .DPS '0' '0' .SWAP '0' b) Shifting Data TSa TSb DD TSc '1' '0' TSc TSd TSd '1' DU CDA10 CDA11 CDA20 CDA21 DD .TSS: TSa TSb .DPS '0' '1' .SWAP '1' c) Switching Data TSa TSb TSc '0' '1' TSc TSd TSd '1' DU CDA10 CDA11 CDA20 CDA21 DD .TSS: TSa TSb .DPS '0' '0' .SWAP '1' Figure 13 TSc '1' '1' TSd '1' Examples for Data Access via CDAxy Registers a) Looping Data b) Shifting (Switching) Data c) Switching and Looping Data Data Sheet 33 2001-03-30 PEF 81912/81913 Functional Description Figure 14 shows the timing of looping TSa from DU to DD via CDAxy register. TSa is read in the CDAxy register from DU and is written one frame later on DD. Figure 15 shows the timing of shifting data from TSa to TSb on DU(DD). In Figure 15a) shifting is done in one frame because TSa and TSb didn't succeed directly one another (a = 0...9 and b a+2). In Figure 15b) shifting is done from one frame to the following frame. This is the case when the time slots succeed one other (b = a+1) or b is smaller than a (b < a). At looping and shifting the data can be accessed by the controller between the synchronous transfer interrupt (STI) and the status overflow interrupt (STOV). STI and STOV are explained in the section 'Synchronous Transfer'. If there is no controller intervention the looping and shifting is done autonomously. *. FSC DU TSa TSa CDAxy STI RD STOV ACK WR C *) DD TSa TSa *) if access by the C is required Figure 14 Data Access when Looping TSa from DU to DD Data Sheet 34 2001-03-30 PEF 81912/81913 Functional Description * a) Shifting TSa TSb within one frame (a,b: 0...11 and b a+2) FSC DU (DD) TSa TSb TSa CDAxy STI RD WR STOV STI C *) b) Shifting TSa TSb in the next frame (a,b: 0...11 and (b = a+1 or b DU (DD) ACK TSa TSb TSa TSb CDAxy STI RD STOV WR C *) *) if access by the C is required ACK Figure 15 Data Access when Shifting TSa to TSb on DU (DD) Data Sheet 35 2001-03-30 PEF 81912/81913 Functional Description Monitoring Data Figure 16 gives an example for monitoring of two IOM(R)-2 time slots each on DU or DD simultaneously. For monitoring on DU and/or DD the channel registers with even numbers (CDA10, CDA20) are assigned to time slots with even numbers TS(2n) and the channel registers with odd numbers (CDA11, CDA21) are assigned to time slots with odd numbers TS(2n+1). The user has to take care of this restriction by programming the appropriate time slots. This mode is only valid if two blocks (e.g. both transceivers) are programmed to these timeslots and communicating via IOM(R)-2. However, if only one block is programmed to this timeslot the timeslots for CDAx0 and CDAx1 can be programmed completely independently. *. a) Monitoring Data EN_O: '0' CDA_CR1. EN_I: '1' DPS: '0' TSS: TS(2n) '0' '1' '0' TS(2n+1) DU CDA10 CDA20 CDA11 CDA21 TSS: TS(2n) DPS: '1' CDA_CR2. EN_I: '1' EN_O: '0' TS(2n+1) '1' '1' '0' DD Figure 16 Example for Monitoring Data Data Sheet 36 2001-03-30 PEF 81912/81913 Functional Description Monitoring TIC Bus Monitoring the TIC bus (TS11) is handled as a special case. The TIC bus can be monitored with the registers CDAx0 by setting the EN_TBM (Enable TIC Bus Monitoring) bit in the control registers CRx. The TSDPx0 must be set to 08h for monitoring from DU or 88h for monitoring from DD. By this it is possible to monitor the TIC bus (TS11) and the odd numbered D-channel (TS3) simultaneously on DU and DD. Synchronous Transfer While looping, shifting and switching the data can be accessed by the controller between the synchronous transfer interrupt (STI) and the synchronous transfer overflow interrupt (STOV). The microcontroller access to each of the CDAxy registers can be synchronized by means of four programmable synchronous transfer interrupts (STIxy)1) and synchronous transfer overflow interrupts (STOVxy)2) in the STI register. Depending on the DPS bit in the corresponding TSDPxy register the STIxy is generated two (for DPS='0') or one (for DPS='1') BCL clock after the selected time slot (CDA_TSDPxy.TSS). One BCL clock is equivalent to two DCL clocks. In the following description the index xy0 and xy1 are used to refer to two different interrupt pairs (STI/STOV) out of the four CDA interrupt pairs (STI10/STOV10, STI11/ STOV11, STI20/STOV20, STI21/STOV21). A STOVxy0 is related to its STIxy0 and is only generated if STIxy0 is enabled and not acknowledged. However, if STIxy0 is masked, the STOVxy0 is generated for any other STIxy1 which is enabled and not acknowledged. Table 10 gives some examples for that. It is assumed that a STOV interrupt is only generated because a STI interrupt was not acknowledged before. In example 1 only the STIxy0 is enabled and thus STIxy0 is only generated. If no STI is enabled, no interrupt will be generated even if STOV is enabled (example 2). In example 3 STIxy0 is enabled and generated and the corresponding STOVxy0 is disabled. STIxy1 is disabled but its STOVxy1 is enabled, and therefore STOVxy1 is generated due to STIxy0. In example 4 additionally the corresponding STOVxy0 is enabled, so STOVxy0 and STOVxy1 are both generated due to STIxy0. In example 5 additionally the STIxy1 is enabled with the result that STOVxy0 is only generated due to STIxy0 and STOVxy1 is only generated due to STIxy1. Compared to the previous example STOVxy0 is disabled in example 6, so STOVxy0 is not generated and STOVxy1 is only generated for STIxy1 but not for STIxy0. 1) In order to enable the STI interrupts the input of the corresponding CDA register has to be enabled. This is also valid if only a synchronous write access is wanted. The enabling of the output alone does not effect an STI interrupt. 2) In order to enable the STOV interrupts the output of the corresponding CDA register has to be enabled. This is also valid if only a synchronous read access is wanted. The enabling of the input alone does not effect an interrupt. Data Sheet 37 2001-03-30 PEF 81912/81913 Functional Description * Table 10 Examples for Synchronous Transfer Interrupts Generated Interrupts (Register STI) STI xy0 xy0 xy0 xy0 xy1 xy0 xy1 xy0 xy1 STOV xy1 xy0 ; xy1 xy0 xy1 xy1 xy0 ; xy2 xy1 ; xy2 Example 1 Example 2 Example 3 Example 4 Example 5 Example 6 Example 7 Enabled Interrupts (Register MSTI) STI xy0 xy0 xy0 xy0 ; xy1 xy0 ; xy1 xy0 ; xy1 STOV xy0 xy1 xy0 ; xy1 xy0 ; xy1 xy1 xy0 ; xy1 ; xy2 Compared to example 5 in example 7 a third STOVxy2 is enabled and thus STOVxy2 is generated additionally for both STIxy0 and STIxy1. A STOV interrupt is not generated if all stimulating STI interrupts are acknowledged. A STIxy must be acknowledged by setting the ACKxy bit in the ASTI register two BCL clock (for DPS='0') or one BCL clocks (for DPS='1') before the time slot which is selected for the appropriate STIxy. The interrupt structure of the synchronous transfer is shown in Figure 17. Data Sheet 38 2001-03-30 PEF 81912/81913 Functional Description *. INT U ST CIC TIN WOV S MOS HDLC MASK Figure 17 U ST CIC TIN WOV S MOS HDLC ISTA STOV21 STOV20 STOV11 STOV10 STI21 STI20 STI11 STI10 MSTI STOV21 STOV20 STOV11 STOV10 STI21 STI20 STI11 STI10 STI ACK21 ACK20 ACK11 ACK10 ASTI Interrupt Structure of the Synchronous Data Transfer Figure 18 shows some examples based on the timeslot structure. Figure a) shows at which point in time a STI and STOV interrupt is generated for a specific timeslot. Figure b) is identical to example 3 above, figure c) corresponds to example 5 and figure d) shows example 4. Data Sheet 39 2001-03-30 PEF 81912/81913 Functional Description *. : STI interrupt generated : STOV interrupt generated for a not acknowledged STI interrupt a) Interrupts for data access to time slot 0 (B1 after reset), MSTI.STI10 and MSTI.STOV10 enabled xy: CDA_TDSPxy.TSS: MSTI.STIxy: MSTI.STOVxy: 10 TS0 '0' '0' 11 TS1 '1' '1' TS2 TS3 21 TS5 '1' '1' TS4 TS5 20 TS11 '1' '1' TS6 TS7 TS8 TS9 TS10 TS11 TS0 TS11 TS0 TS1 b) Interrupts for data access to time slot 0 (B1 after reset), STOV interrupt used as flag for "last possible CDA access"; MSTI.STI10 and MSTI.STOV20 enabled xy: CDA_TDSPxy.TSS: MSTI.STIxy: MSTI.STOVxy: 10 TS0 '0' '1' 11 TS1 '1' '1' TS2 TS3 21 TS5 '1' '1' TS4 TS5 20 TS11 '1' '0' TS6 TS7 TS8 TS9 TS10 TS11 TS0 TS11 TS0 TS1 c) Interrupts for data access to time slot 0 and 1 (B1 and B2 after reset), MSTI.STI10, MSTI.STOV10, MSTI.STI11 and MSTI.STOV11 enabled xy: CDA_TDSPxy.TSS: MSTI.STIxy: MSTI.STOVxy: 10 TS0 '0' '0' 11 TS1 '0' '0' TS2 TS3 21 TS5 '1' '1' TS4 TS5 20 TS11 '1' '1' TS6 TS7 TS8 TS9 TS10 TS11 TS0 TS11 TS0 TS1 d) Interrupts for data access to time slot 0 (B1 after reset), STOV20 interrupt used as flag for "last possible CDA access", STOV10 interrupt used as flag for "CDA access failed"; MSTI.STI10, MSTI.STOV10 and MSTI.STOV20 enabled xy: CDA_TDSPxy.TSS: MSTI.STIxy: MSTI.STOVxy: 10 TS0 '0' '0' 11 TS1 '1' '1' TS2 TS3 21 TS5 '1' '1' TS4 TS5 20 TS11 '1' '0' TS6 TS7 TS8 TS9 TS10 TS11 TS0 TS11 TS0 TS1 sti_stov.vsd Figure 18 * . Examples for the Synchronous Transfer Interrupt Control with one STIxy enabled Data Sheet 40 2001-03-30 PEF 81912/81913 Functional Description 2.3.2.2 Serial Data Strobe Signal For time slot oriented standard devices at the IOM(R)-2 interface, the Q-SMINT(R)IX provides two independent data strobe signals SDS1 and SDS2. The two strobe signals can be generated with every 8-kHz-frame and are controlled by the registers SDS1/2_CR. By programming the TSS bits and three enable bits (ENS_TSS, ENS_TSS+1, ENS_TSS+3) a data strobe can be generated for the IOM(R)-2 time slots TS, TS+1 and TS+3 (bit7,6) and the combinations of them. The data strobes for TS and TS+1 are always 8 bits long (bit7 to bit0) whereas the data strobe for TS+3 is always 2 bits long (bit7, bit6). * FSC DD,DU MM RX MM RX B1 TS0 B2 TS1 MON0 TS2 D CI0 IC1 TS4 IC2 MON1 TS5 TS6 CI1 TS3 TS7 TS8 TS9 TS10 TS11 TS0 TS1 SDS1,2 (Example1) SDS1,2 (Example2) SDS1,2 (Example3) Example 1: TSS ENS_TSS ENS_TSS+1 ENS_TSS+3 TSS ENS_TSS ENS_TSS+1 ENS_TSS+3 TSS ENS_TSS ENS_TSS+1 ENS_TSS+3 = '0H' = '0' = '1' = '0' = '5H' = '1' = '1' = '0' = '0H' = '1' = '1' = '1' strobe.vsd Example 2: Example 3: Figure 19 Data Strobe Signal Generation Data Sheet 41 2001-03-30 PEF 81912/81913 Functional Description Figure 19 shows three examples for the generation of a strobe signal. In example 1 the SDS is active during channel B2 on IOM(R)-2, whereas in the second example during IC2 and MON1. The third example shows a strobe signal for 2B+D channels which is used e.g. at an IDSL (144 kbit/s) transmission. 2.3.3 IOM(R)-2 Monitor Channel The IOM(R)-2 MONITOR channel is utilized for information exchange between the QSMINT(R)IX and other devices in the MONITOR channel. The MONTIOR channel data can be controlled by the bits in the MONITOR control register (MON_CR). For the transmission of the MONITOR data one of the 3 IOM(R)-2 channels can be selected by setting the MONITOR channel selection bits (MCS) in the MONITOR control register (MON_CR). The DPS bit in the same register selects between an output on DU or DD respectively and with EN_MON the MONITOR data can be enabled/disabled. The default value is MONITOR channel 0 (MON0) enabled and transmission on DD. The MONITOR channel of the Q-SMINT(R)IX can be used in the following applications (refer also to Figure 4 and Figure 5): * As a master device the Q-SMINT(R)IX can program and control other devices (e.g. PSB 2161) attached to the IOM(R)-2, which therefore, do not need a microcontroller interface. * As a slave device the Q-SMINT(R)IX is programmed and controlled from a master device on IOM(R)-2 (e.g. UTAH). This is used in applications where no microcontroller is connected directly to the Q-SMINT(R)IX. The MONITOR channel operates according to the IOM(R)-2 Reference Guide [13]. Note: In contrast to the INTC-Q, the Q-SMINT(R)IX does neither issue nor react on Monitor commands (MON0,1,2,8). Instead, the Q-SMINT(R)IX operated in IOM(R)-2 slave mode must be programmed via new MONITOR channel concept (see Chapter 2.3.3.4), which provides full register access. The Monitor time out procedure is available. Reporting of the Q-SMINT(R)IX is performed via interrupts. 2.3.3.1 Handshake Procedure The MONITOR channel operates on an asynchronous basis. While data transfers on the bus take place synchronized to frame sync, the flow of data is controlled by a handshake procedure using the MONITOR Channel Receive (MR) and MONITOR Channel Transmit (MX) bits. Data is placed onto the MONITOR channel and the MX bit is activated. This data will be transmitted once per 8-kHz frame until the transfer is acknowledged via the MR bit. Data Sheet 42 2001-03-30 PEF 81912/81913 Functional Description The MONITOR channel protocol is described In the following section and Figure 22 shall illustrate this. The relevant control and status bits for transmission and reception are listed in Table 11 and Table 12. Table 11 Control/ Status Bit Control Status Transmit Direction Register MOCR MOSR MSTA Table 12 Control/ Status Bit Control Status Bit MXC MIE MDA MAB MAC Function MX Bit Control Transmit Interrupt (MDA, MAB, MER) Enable Data Acknowledged Data Abort Transmission Active Receive Direction Register MOCR MOSR Bit MRC MRE MDR MER Function MR Bit Control Receive Interrupt (MDR) Enable Data Received End of Reception Data Sheet 43 2001-03-30 PEF 81912/81913 Functional Description * P Transmitter MON MX 1 1 0 0 1 0 0 0 1 0 0 0 1 1 1 1 Receiver MR 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 1 ITD10032 P MIE = 1 MOX = ADR MXC = 1 MAC = 1 MDA Int. MOX = DATA1 FF FF ADR ADR DATA1 DATA1 DATA1 DATA1 DATA2 DATA2 DATA2 DATA2 FF FF FF FF 125 s MDR Int. RD MOR (=ADR) MRC = 1 MDR Int. RD MOR (=DATA1) MDA Int. MOX = DATA2 MDR Int. RD MOR (=DATA2) MDA Int. MXC = 0 MER Int. MRC = 0 MAC = 0 Figure 20 MONITOR Channel Protocol (IOM(R)-2) Before starting a transmission, the microprocessor should verify that the transmitter is inactive, i.e. that a possible previous transmission has been terminated. This is indicated by a '0' in the MONITOR Channel Active MAC status bit. After having written the MONITOR Data Transmit (MOX) register, the microprocessor sets the MONITOR Transmit Control bit MXC to '1'. This enables the MX bit to go active (0), indicating the presence of valid MONITOR data (contents of MOX) in the corresponding frame. As a result, the receiving device stores the MONITOR byte in its MONITOR Receive MOR register and generates a MDR interrupt status. Alerted by the MDR interrupt, the microprocessor reads the MONITOR Receive (MOR) register. When it is ready to accept data (e.g. based on the value in MOR, which in a point-to-multipoint application might be the address of the destination device), it sets the MR control bit MRC to '1' to enable the receiver to store succeeding MONITOR channel bytes and acknowledge them according to the MONITOR channel protocol. Data Sheet 44 2001-03-30 PEF 81912/81913 Functional Description In addition, it enables other MONITOR channel interrupts by setting MONITOR Interrupt Enable (MIE) to '1'. As a result, the first MONITOR byte is acknowledged by the receiving device setting the MR bit to '0'. This causes a MONITOR Data Acknowledge MDA interrupt status at the transmitter. A new MONITOR data byte can now be written by the microprocessor in MOX. The MX bit is still in the active (0) state. The transmitter indicates a new byte in the MONITOR channel by returning the MX bit active after sending it once in the inactive state. As a result, the receiver stores the MONITOR byte in MOR and generates a new MDR interrupt status. When the microprocessor has read the MOR register, the receiver acknowledges the data by returning the MR bit active after sending it once in the inactive state. This in turn causes the transmitter to generate a MDA interrupt status. This "MDA interrupt - write data - MDR interrupt - read data - MDA interrupt" handshake is repeated as long as the transmitter has data to send. Note that the MONITOR channel protocol imposes no maximum reaction times to the microprocessor. When the last byte has been acknowledged by the receiver (MDA interrupt status), the microprocessor sets the MONITOR Transmit Control bit MXC to '0'. This enforces an inactive ('1') state in the MX bit. Two frames of MX inactive signifies the end of a message. Thus, a MONITOR Channel End of Reception MER interrupt status is generated by the receiver when the MX bit is received in the inactive state in two consecutive frames. As a result, the microprocessor sets the MR control bit MRC to 0, which in turn enforces an inactive state in the MR bit. This marks the end of the transmission, making the MONITOR Channel Active MAC bit return to '0'. During a transmission process, it is possible for the receiver to ask a transmission to be aborted by sending an inactive MR bit value in two consecutive frames. This is effected by the microprocessor writing the MR control bit MRC to '0'. An aborted transmission is indicated by a MONITOR Channel Data Abort MAB interrupt status at the transmitter. The MONITOR transfer protocol rules are summarized in the following section * A pair of MX and MR in the inactive state for two or more consecutive frames indicates an idle state or an end of transmission. * A start of a transmission is initiated by the transmitter by setting the MXC bit to '1' enabling the internal MX control. The receiver acknowledges the received first byte by setting the MR control bit to '1' enabling the internal MR control. * The internal MX, MR control indicates or acknowledges a new byte in the MON slot by toggling MX, MR from the active to the inactive state for one frame. * Two frames with the MR-bit set to inactive indicate a receiver request for abort. * The transmitter can delay a transmission sequence by sending the same byte continuously. In that case the MX-bit remains active in the IOM(R)-2 frame following the first byte occurrence. Delaying a transmission sequence is only possible while the receiver MR-bit and the transmitter MX-bit are active. Data Sheet 45 2001-03-30 PEF 81912/81913 Functional Description * Since a double last-look criterion is implemented the receiver is able to receive the MON slot data at least twice (in two consecutive frames), the receiver waits for the acknowledge of the reception of two identical bytes in two successive frames. * To control this handshake procedure a collision detection mechanism is implemented in the transmitter. This is done by making a collision check per bit on the transmitted MONITOR data and the MX bit. * Monitor data will be transmitted repeatedly until its reception is acknowledged or the transmission time-out timer expires. * Two frames with the MX bit in the inactive state indicates the end of a message (EOM). * Transmission and reception of monitor messages can be performed simultaneously. This feature is used by the device to send back the response before the transmission from the controller is completed (the device does not wait for EOM from controller). 2.3.3.2 Error Treatment In case the device does not detect identical monitor messages in two successive frames, transmission is not aborted. Instead the device will wait until two identical bytes are received in succession. A transmission is aborted by the device if * an error in the MR handshaking occurs * a collision on the IOM(R)-2 bus of the MONITOR data or MX bit occurs * the transmission time-out timer expires A reception is aborted by the device if * an error in the MX handshaking occurs or * an abort request from the opposite device occurs MX/MR Treatment in Error Case In the master mode the MX/MR bits are under control of the microcontroller through MXC or MRC, respectively. An abort is indicated by an MAB interrupt or MER interrupt, respectively. In the slave mode the MX/MR bits are under control of the device. An abort is always indicated by setting the MX/MR bit inactive for two or more IOM(R)-2 frames. The controller must react with EOM. Figure 21 shows an example for an abort requested by the receiver, Figure 22 shows an example for an abort requested by the transmitter and Figure 23 shows an example for a successful transmission. Data Sheet 46 2001-03-30 PEF 81912/81913 Functional Description * IOM -2 Frame No. MX (DU) 1 1 2 3 4 5 6 EOM 7 0 MR (DD) 1 0 Abort Request from Receiver mon_rec-abort.vsd Figure 21 * Monitor Channel, Transmission Abort requested by the Receiver IOM -2 Frame No. MR (DU) 1 1 2 3 4 5 6 EOM 7 0 MX (DD) 1 0 Abort Request from Transmitter mon_tx-abort.vsd Figure 22 * Monitor Channel, Transmission Abort requested by the Transmitter IOM -2 Frame No. MR (DU) 1 1 2 3 4 5 6 7 EOM 8 0 MX (DD) 1 0 mon_norm.vsd Figure 23 Data Sheet Monitor Channel, Normal End of Transmission 47 2001-03-30 PEF 81912/81913 Functional Description 2.3.3.3 MONITOR Channel Programming as a Master Device The master mode is selected by default if one of the microcontroller interfaces is selected. The monitor data is written by the microcontroller in the MOX register and transmitted via IOM(R)-2 DD(DU) line to the programmed/controlled device e.g. ARCOFIBA PSB 2161. The transfer of the commands in the MON channel is regulated by the handshake protocol mechanism with MX, MR. 2.3.3.4 MONITOR Channel Programming as a Slave Device MONITOR slave mode can be selected by pinstrapping the microcontroller interface pins according to Table 5. All programming data required by the device is received in the MONITOR time slot on the IOM(R)-2 and is transferred to the MOR register. The transfer of the commands in the MON channel is regulated by the handshake protocol mechanism with MX, MR which is described in the previous Chapter 2.3.3.1. The first byte of the MONITOR message must contain in the higher nibble the MONITOR channel address code which is '1000' for the Q-SMINT(R)IX. The lower nibble distinguishes between a programming command and an identification command. Identification Command In order to be able to identify unambiguously different hardware designs of the QSMINT(R)IX by software, the following identification command is used: DU 1st byte value DU 2nd byte value 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The Q-SMINT(R)IX responds to this identification sequence by sending a identification sequence: DD 1st byte value DD 2nd byte value 1 0 0 0 0 0 0 0 0 0 DESIGN DESIGN: six bit code, specific for each device in order to identify differences in operation (see "ID - Identification Register" on Page 198). This identification sequence is usually done once, when the Q-SMINT(R)IX is connected for the first time. This function is used so that the software can distinguish between different possible hardware configurations. However this sequence is not compulsory. Programming Sequence The programming sequence is characterized by a '1' being sent in the lower nibble of the received address code. The data structure after this first byte is equivalent to the structure of the serial control interface described in chapter Chapter 2.1.1. Data Sheet 48 2001-03-30 PEF 81912/81913 Functional Description * DU 1st byte value DU 2nd byte value DU 3rd byte value DU 4th byte value DU (nth + 3) byte value 1 R/W 0 0 0 0 0 0 1 Header Byte Command/ Register Address Data 1 Data n All registers can be read back when setting the R/W bit to '1'. The Q-SMINT(R)IX responds by sending his IOM(R)-2 specific address byte (81h) followed by the requested data. Note: Application Hint: It is not allowed to disable the MX- and MR-control in the programming device at the same time! First, the MX-control must be disabled, then the C has to wait for an End of Reception before the MR-control may be disabled. Otherwise, the QSMINT(R)IX does not recognize an End of Reception. 2.3.3.5 Monitor Time-Out Procedure To prevent lock-up situations in a MONITOR transmission a time-out procedure can be enabled by setting the time-out bit (TOUT) in the MONITOR configuration register (MCONF). An internal timer is always started when the transmitter must wait for the reply of the addressed device or for transmit data from the microcontroller. After 40 IOM(R)-2 frames (5 ms) without reply the timer expires and the transmission will be aborted with an EOM (End of Message) command by setting the MX bit to '1' for two consecutive IOM(R)-2 frames. 2.3.3.6 MONITOR Interrupt Logic Figure 24 shows the interrupt structure of the MONITOR handler. The MONITOR Data Receive interrupt status MDR has two enable bits, MONITOR Receive interrupt Enable (MRE) and MR bit Control (MRC). The MONITOR channel End of Reception MER, MONITOR channel Data Acknowledged MDA and MONITOR channel Data Abort MAB interrupt status bits have a common enable bit MONITOR Interrupt Enable MIE. MRE set to "0" prevents the occurrence of MDR status, including when the first byte of a packet is received. When MRE is set to "1" but MRC is set to "0", the MDR interrupt status is generated only for the first byte of a receive packet. When both MRE and MRC are set to "1", MDR is always generated and all received MONITOR bytes - marked by a 1-to-0 transition in MX bit - are stored. Additionally, a MRC set to "1" enables the control of the MR handshake bit according to the MONITOR channel protocol. Data Sheet 49 2001-03-30 PEF 81912/81913 Functional Description * MASK U ST CIC TIN WOV S MOS HDLC ISTA U ST CIC TIN WOV S MOS HDLC MRE MIE MOCR MDR MER MDA MAB MOSR INT Figure 24 MONITOR Interrupt Structure 2.3.4 C/I Channel Handling The Command/Indication channel carries real-time status information between the QSMINT(R)IX and another device connected to the IOM(R)-2. 1) C/I0 channel lies in IOM(R)-2 channel 0 and access may be arbitrated via the TIC bus access protocol. In this case the arbitration is done in IOM(R)-2 channel 2. The C/I0 channel is accessed via register CIR0 (received C/I0 data from DD) and register CIX0 (transmitted C/I0 data to DU). The C/I0 code is four bits long. In the receive direction, the code from layer-1 is continuously monitored, with an interrupt being generated any time a change occurs (ISTA.CIC). C/I0 only: a new code must be found in two consecutive IOM(R)-2 frames to be considered valid and to trigger a C/I code change interrupt status (double last look criterion). In the transmit direction, the code written in CIX0 is continuously transmitted in C/I0. 2) A second C/I channel (called C/I1) lies in IOM(R)-2 channel 1 and is used to convey real time status information of the on-chip S-transceiver or an external device. The C/I1 channel consists of four or six bits in each direction. The width can be changed from 4 bit to 6 bit by setting bit CIX1.CICW. In 4-bit mode 6-bits are written whereby the higher 2 bits must be set to "1" and 6-bits are read whereby only the 4 LSBs are used for comparison and interrupt generation (i.e. the higher two bits are ignored). Data Sheet 50 2001-03-30 PEF 81912/81913 Functional Description The C/I1 channel is accessed via registers CIR1 and CIX1. The connection of CIR1 and CIX1 to DD and DU, respectively, can be selected by setting bit HCI_CR.DPS_CI1. A change in the received C/I1 code is indicated by an interrupt status without double last look criterion. CIC Interrupt Logic Figure 25 shows the CIC interrupt structure. The two corresponding status bits CIC0 and CIC1 are read in CIR0 register. CIC1 can be individually disabled by clearing the enable bit CI1E in the CIX1 register. In this case the occurrence of a code change in CIR1 will not be displayed by CIC1 until the corresponding enable bit has been set to one. Bits CIC0 and CIC1 are cleared by a read of CIR0. An interrupt status is indicated every time a valid new code is loaded in CIR0 or CIR1. The CIR0 is buffered with a FIFO size of two. If a second code change occurs in the received C/I channel 0 before the first one has been read, immediately after reading of CIR0 a new interrupt will be generated and the new code will be stored in CIR0. If several consecutive codes are detected, only the first and the last code are obtained at the first and second register read, respectively. For CIR1 no FIFO is available. The actual code of the received C/I channel 1 is always stored in CIR1. * MASK U ST CIC TIN WOV S MOS HDLC ISTA U ST CIC TIN WOV S MOS HDLC CI1E CIX1 CIC0 CIC1 CIR0 INT Figure 25 CIC Interrupt Structure 2.3.5 D-Channel Access Control The upstream D-channel is arbitrated between the S-bus, the internal HDLC controller and external HDLC controllers via the TIC bus (S/G, BAC, TBA bits) according to the Data Sheet 51 2001-03-30 PEF 81912/81913 Functional Description IOM(R)-2 Reference Guide1). Further to the implementation in the INTC-Q it is possible, to set the priority (8 or 10) of all HDLC-controllers connected to IOM(R)-2, which is particularly useful for use of the Q-SMINT(R)IX together with the UTAH. 2.3.5.1 Application Example for D-Channel Access Control Figure 26 shows a scenario for the local D-channel arbitration between the S-bus and the microcontroller. * Q-SMINT(R)IX E-Bit D BAC, TBA S Arbitr. Prio S/G U HDLC CIX0 CIR0 D IOM-2 i/f P - i/f C e.g. C513, C161-RI IOM-2 C writes data into FIFO, transmission happens.automatically Q-SMINTIX delivers an interrupt, when transmission is complete Figure 26 D-Channel Arbitration: C has no HDLC and no Direct Access to TIC Bus 2.3.5.2 TIC Bus Handling The TIC bus is implemented to organize the access to the C/I0-channel and to the Dchannel from up to 7 D-channels HDLC controllers. The arbitration mechanism must be activated by setting MODEH.DIM2-0=00x. The arbitration mechanism is implemented in the last octet in IOM(R)-2 channel 2 of the IOM(R)-2 interface (see Figure 27). An access request to the TIC bus may either be generated by software (C access to the C/I0-channel via CIX0 register) or by an internal or an external D-channel HDLC controller (transmission of an HDLC frame in the Dchannel). A software access request to the bus is effected by setting the BAC bit in register CIX0 to '1' (resulting in BAC = '0' on IOM(R)-2). 1) The A/B-bit is not supported by the U-transceiver Data Sheet 52 2001-03-30 PEF 81912/81913 Functional Description In the case of an access request by the Q-SMINT(R)IX, the Bus Accessed-bit BAC (bit 5 of last octet of CH2 on DU, see Figure 27) is checked for the status "bus free", which is indicated by a logical '1'. If the bus is free, the Q-SMINT(R)IX transmits its individual TIC bus address TAD programmed in the CIX0 register (CIX0.TBA2-0). While being transmitted the TIC bus address TAD is compared bit by bit with the value read back on DU. If a sent bit set to '1' is read back as '0' because of the access of an external device with a lower TAD, the Q-SMINT(R)IX withdraws immediately from the TIC bus, i.e. the remaining TAD bits are not transmitted. The TIC bus is occupied by the device which sends and reads back its address error-free. If more than one device attempt to seize the bus simultaneously, the one with the lowest address values wins. This one will set BAC=0 on TIC bus and starts D-channel transmission in the same frame. * MR MX MR MX IC2 MON1 CI1 TAD BAC DU B1 B2 MON0 D CI0 IC1 BAC 2 TAD 1 0 ITD02575.vsd TIC-BUS Address (TAD 2 - 0) Bus Accessed ("1" no TIC-BUS Access) Figure 27 Structure of Last Octet of Ch2 on DU When the TIC bus is seized by the Q-SMINT(R)IX, the bus is identified to other devices as occupied via the DU Ch2 Bus Accessed-bit state '0' until the access request is withdrawn. After a successful bus access, the Q-SMINT(R)IX is automatically set into a lower priority class, that is, a new bus access cannot be performed until the status "bus free" is indicated in two successive frames. If none of the devices connected to the IOM(R)-2 interface request access to the D and C/ I0 channels, the TIC bus address 7 will be present. The device with this address will therefore have access, by default, to the D and C/I0 channels. Note: Bit BAC (CIX0 register) should be reset by the C when access is no more requested, to grant other devices access to the D and C/I0 channels. 2.3.5.3 Stop/Go Bit Handling The availability of the DU D channel is indicated in bit 5 "Stop/Go" (S/G) of the last octet in DD channel 2 (Figure 28). The arbitration mechanism must be activated by setting MODEH.DIM2-0=0x1. S/G = 1 : stop S/G = 0 : go Data Sheet 53 2001-03-30 PEF 81912/81913 Functional Description The Stop/Go bit is available to other layer-2 devices connected to the IOM(R)-2 interface to determine if they can access the D channel in upstream direction. * MR MX MR MX IC2 MON1 CI1 S/G A/B DD B1 B2 MON 0 D CI0 IC1 S/G A/B Stop/Go Available/Blocked ITD09693.vsd Figure 28 Structure of Last Octet of Ch2 on DD 2.3.5.4 D-Channel Arbitration In intelligent NT applications (selected via register S_MODE.MODE2-0) the QSMINT(R)IX has to share the upstream D-channel with one or more D-channel controllers on the IOM(R)-2 interface and with all connected TEs on the S interface. The S-transceiver incorporates an elaborate state machine for D-channel priority handling on IOM(R)-2 (Chapter 2.3.5.5). For the access to the D-channel a similar arbitration mechanism as on the S interface (writing D-bits, reading back E-bits) is performed for all D-channel sources on IOM(R)-2. Due to this an equal and fair access is guaranteed for all D-channel sources on both the S interface and the IOM(R)-2 interface. The access to the upstream D-channel is handled via the S/G bit for the HDLC controllers and via E-bit for all connected terminals on S (E-bits are inverted to block the terminals on S). Furthermore, if more than one HDLC source is requesting D-channel access on IOM(R)-2 the TIC bus mechanism is used (see Chapter 2.3.5.2). The arbiter permanently counts the "1s" in the upstream D-channel on IOM(R)-2. If the necessary number of "1s" is counted and an HDLC controller on IOM(R)-2 requests upstream D-channel access (BAC bit is set to 0), the arbiter allows this D-channel controller immediate access and blocks other TEs on S (E-bits are inverted). Similar as on the S-interface the priority for D-channel access on IOM(R)-2 can be configured to 8 or 10 (S_CMD.DPRIO). The configuration settings of the Q-SMINT(R)IX in intelligent NT applications are summarized in Table 13. Data Sheet 54 2001-03-30 PEF 81912/81913 Functional Description * Table 13 Q-SMINT(R)IX Configuration Settings in Intelligent NT Applications Configuration Setting S-Transceiver Mode Register: S_MODE.MODE0 = 0 (NT state machine) or S_MODE.MODE0 = 1 (LT-S state machine) S_MODE.MODE1 = 1 S_MODE.MODE2 = 1 Functional Configuration Block Description Layer 1 Select Intelligent NT mode Layer 2 Enable S/G bit and TIC bus evaluation D-channel Mode Register: MODEH.DIM2-0 = 001 Note: For mode selection in the S_MODE register the MODE1/2 bits are used to select intelligent NT mode, MODE0 selects NT or LT-S state machine. With the configuration settings shown above the Q-SMINT(R)IX in intelligent NT applications provides for equal access to the D-channel for terminals connected to the S-interface and for D-channel sources on IOM(R)-2. 2.3.5.5 State Machine of the D-Channel Arbiter Figure 29 gives a simplified view of the state machine of the D-channel arbiter. CNT is the number of '1' on the IOM(R)-2 D-channel and BAC corresponds to the BAC-bit on IOM(R)-2. The number n depends on configuration settings (selected priority 8 or 10) and the condition of the previous transmission, i.e. if an abort was seen (n = 8 or 10, respectively) or if the last transmission was successful (n = 9 or 11, respectively). Data Sheet 55 2001-03-30 PEF 81912/81913 Functional Description * RST=0, A/B=0, Mode=0xx IN BAC OUT State S/G CNT 6 E DCI BAC = 1 & DCI = 0 (CNT 2 & D=0) & [BAC = 1 or (BAC = 0 & CNT < n)] READY S/G = 1 E = D 1)2) (BAC=1 & DCI=0) (BAC=0 or DCI=1) & CNT n BAC = d.c. DCI = d.c. LOCAL ACCESS Transmit / Stop Flag S/G = 0 E=D CNT = 6 BAC = 0 or DCI = 1 BAC = d.c. DCI = 0 S ACCESS S/G = 1 E = D1) 1) Setting DCI = 1 causes E = D 2) Setting A/B = 0 causes E = D D-Channel_Arbitration.vsd LOCAL ACCESS Wait for Start Flag S/G = 0 E=D Figure 29 State Machine of the D-Channel Arbiter (Simplified View)1) Table 14 lists the major differences of the D-channel arbiters state machine between QSMINT(R)IX and INTC-Q [12] *: Table 14 State 'IDLE' (S/G=0, E=D) BAC-bit Major Differences D-Channel Arbiter INTC-Q and Q-SMINT(R)IX INTC-Q Automatically entered from state 'READY' or 'S ACCESS' after CNT=n Ignored Q-SMINT(R)IX Not available, initial state is 'READY' (S/G=1, E=D) Local HDLC must tie BAC = '0' to enter state 'LOCAL ACCESS' S-MODE.DCH_INH Alternative to BAC-bit to enter state 'LOCAL ACCESS' D-channel inhibit Not possible 1) If the S-transceiver is reset by SRES.RES_S = '1' or disabled by S_CONF0.DIS_TR = '1', then the D-channel arbiter is in state Ready (S/G = '1'), too. The S/G evaluation of the HDLC has to be disabled in this case; otherwise, the HDLC is not able to send data. Data Sheet 56 2001-03-30 PEF 81912/81913 Functional Description 1. Local D-Channel Controller Transmits Upstream In the initial state ('Ready' state) neither the local D-channel sources nor any of the terminals connected to the S-bus transmit in the D-channel. The Q-SMINT(R)IX S-transceiver thus receives BAC = "1" (IOM(R)-2 DU line) and transmits S/G = "1" (IOM(R)-2 DD line). The access will then be established according to the following procedure: * Local D-channel source verifies that BAC bit is set to ONE (currently no bus access). * Local D-channel source issues TIC bus address and verifies that no controller with higher priority requests transmission (TIC bus access must always be performed even if no other D-channel sources are connected to IOM(R)-2). * Local D-channel source issues BAC = "0" to block other sources on IOM(R)-2 and to announce D-channel access. * Q-SMINT(R)IX S-transceiver pulls S/G bit to ZERO ('Local Access' state) as soon as CNT n (see note) to allow sending D-channel data from the entitled source. Q-SMINT(R)IX S-transceiver transmits inverted echo channel (E bits) on the S-bus to block all connected S-bus terminals (E = D). * Local D-channel source commences with D data transmission on IOM(R)-2 as long as it receives S/G = "0". * After D-channel data transmission is completed the controller sets the BAC bit to ONE. * Q-SMINT(R)IX S-transceiver transmits non-inverted echo (E = D). * Q-SMINT(R)IX S-transceiver pulls S/G bit to ONE ('Ready' state) to block the D-channel controller on IOM(R)-2. Note: If right after D-data transmission the D-channel arbiter goes to state 'Ready' and the local D-channel source wants to transmit again, then it may happen that the leading '0' of the start flag is written into the D-channel before the D-channel source recognizes that the S/G bit is pulled to '1' and stops transmission. In order to prevent unintended transitions to state 'S-Access', the additional condition CNT 2 is introduced. As soon as CNT n, the S/G bit is set to '0' and the D-channel source may start transmission again (if TIC bus is occupied). This allows an equal access for D-channel sources on IOM(R)-2 and on the S interface. 2. Terminal Transmits D-Channel Data Upstream The initial state is identical to that described in the last paragraph. When one of the connected S-bus terminals needs to transmit in the D-channel, access is established according to the following procedure: * S-transceiver recognizes that the D-channel on the S-bus is active via D = '0'. * S-transceiver transfers S-bus D-channel data transparently through to the upstream IOM(R)-2 bus. Data Sheet 57 2001-03-30 PEF 81912/81913 Functional Description 2.3.6 Activation/Deactivation of IOM(R)-2 Interface The deactivation procedure of the IOM(R)-2 interface is shown in Figure 30. After detecting the code DI (Deactivation Indication) the Q-SMINT(R)IX responds by transmitting DC (Deactivation Confirmation) during subsequent frames and stops the timing signals after the fourth frame. The clocks stop at the end of the C/I-code in IOM(R)2 channel 0. * a) FSC DI DIN DR DOUT DR DC DC DC DC DI DI DI DI DI IOM -2 Interface deactivated R Detail see Fig.b b) DCL IOM -2 Interface deactivated R DIN D C/ C/ C/ C/ ITD10292 Figure 30 Deactivation of the IOM(R)-2 Clocks Conditions for Power-Down If none of the following conditions is true, the IOM(R)-2 interface can be switched off, reducing power consumption to a minimum. * * * * * * * S-transceiver is not in state 'Deactivated' Signal INFO0 on the S-interface Uk0-transceiver is not in state 'Deactivated' Pin DU is low (either at the IOM(R)-2 interface or via IOM_CR.SPU) External pin EAW External Awake is low Bit MODE 1.CFS = '0' Stop on the correct place in the IOM(R)-2 frame. DCL must be low during power down (stop on falling edge of DCL) (see Figure 30). Data Sheet 58 2001-03-30 PEF 81912/81913 Functional Description A deactivated IOM(R)-2 can be reactivated by one of the following methods: * Pulling pin DU line low: - directly at the IOM(R)-2 interface - via the P interface with "Software Power Up" (IOM_CR:SPU bit) * Pulling pin EAW `External Awake` low * Setting `Configuration Select` MODE1:CFS bit = '0' * Level detection at the S-interface * Activation from the U-interface Data Sheet 59 2001-03-30 PEF 81912/81913 Functional Description 2.4 U-Transceiver The state machine of the U-Transceiver is based on the NT state machine in the PEB / PEF 8191 documentation [12]. Note: 'Self test request' and 'Self test passed' are not executed by the U-transceiver The U-transceiver is configured and controlled via the registers described in Chapter 4.11. The U-transceiver is always in IOM(R)-2 channel 0. It is possible to select between a state machine that simplifies programming (see Chapter 2.4.10.6) and the state machine as known from the PEB / PEF 8091 (see Chapter 2.4.10.2). 2.4.1 2B1Q Frame Structure Transmission on the U2B1Q-interface is performed at a rate of 80 kbaud. The code used is reducing two bits to one quaternary symbol (2B1Q). Data is grouped together into U-superframes of 12 ms each. Each superframe consists of eight basic frames which begin with a synchronization word and contain 222 bits of information. The first basic frame of a superframe starts with an inverted synchword (ISW) compared to the other basic frames (SW). The structure of one U-superframe is illustrated in Figure 31 and Figure 32. ISW 1. Basic Frame SW 2. Basic Frame ... SW 8. Basic Frame <---12 ms---> Figure 31 * * U-Superframe Structure 12 x 2B + D User Data 216 Bits (108 Quat) (I) SW (Inverted) Synch Word 18 Bit (9 Quat) <---1,5 ms---> Figure 32 M1 - M6 Maintenance Data 6 Bits (3 Quat) U-Basic Frame Structure Out of the 222 information bits 216 contain 2B + D data from 12 IOM(R)-frames, the remaining 6 bits are used to transmit maintenance information. Thus 48 maintenance bits are available per U-superframe. They are used to transmit two EOC-messages (24 bit), 12 Maintenance (overhead) bits and one checksum (12 bit). Data Sheet 60 2001-03-30 PEF 81912/81913 Functional Description * Table 15 U-Superframe Format Framing Quat Position s Bit Position s 1-9 2B + D 10 - 117 19 - 234 Overhead Bits (M1 - M6) 118 s 118 m 119 s 119 m 120 s 120 m 1 - 18 235 236 237 238 239 240 Super Basic Sync Frame # Frame # Word 1 1 2 3 4 5 6 7 8 2,3... ISW SW SW SW SW SW SW SW 2B + D 2B + D 2B + D 2B + D 2B + D 2B + D 2B + D 2B + D 2B + D M1 EOC a1 EOC dm EOC i3 EOC i6 EOC a1 EOC dm EOC i3 EOC i6 M2 EOC a2 EOC i1 EOC i4 EOC i7 EOC a2 EOC i1 EOC i4 EOC i7 M3 EOC a3 EOC i2 EOC i5 EOC i8 EOC a3 EOC i2 EOC i5 EOC i8 M4 ACT/ ACT DEA / PS1 SCO/ PS2 M5 1 1 M6 1 FEBE CRC1 CRC2 1/ NTM CRC3 CRC4 1/ CSO CRC5 CRC6 1 UOA / SAI AIB / NIB CRC7 CRC8 CRC9 CRC 10 CRC 11 CRC 12 LT- to NT dir. > / - - - - ISW SW CRC EOC Inverted Synchronization Word (quad): Synchronization Word (quad): Cyclic Redundancy Check Embedded Operation Channel a d/m i Activation bit ACT < NT- to LT dir. -3-3+3+3+3-3+3-3-3 +3+3-3-3-3+3-3+3+3 = address bit = data / message bit = information (data / message) = (1) -> Layer 2 ready for communication 2001-03-30 - ACT Data Sheet 61 PEF 81912/81913 Functional Description - - - - - - - - - - - - DEA CSO UOA SAI FEBE PS1 PS2 NTM AIB NIB SCO 1 Deactivation bit DEA Cold Start Only CSO U-Only Activation UOA S-Activity Indicator SAI Far-end Block Error FEBE Power Status Primary Source PS1 Power Status Secondary Source PS2 NT-Test Mode NTM Alarm Indication Bit AIB Network Indication Bit NIB Start on Command only bit (currently not defined by ANSI/ETSI) = (0) -> LT informs NT that it will turn off = (1) -> NT-activation with cold start only = (0) -> U-only activated = (0) -> S-interface is deactivated = (0) -> Far-end block error occurred = (1) -> Primary power supply ok = (1) -> Secondary power supply ok = (0) -> NT busy in test mode = (0) -> Interruption (according to ANSI) = (1) -> no function (reserved for network use) can be accessed by the system interface for proprietary use The principle signal flow is depicted in Figure 33 and Figure 34. The data is first grouped in bits that are covered by the CRC and bits that are not. After the CRC generation the bits are arranged in the proper sequence according to the 2B1Q frame format, encoded and finally transmitted. In receive direction the data is first decoded, descrambled, deframed and handed over for further processing. * Tone/Pulse Patterns M U X (M-bit handling acc. to ETR080) U2B1Q-Fram e r Sy nc/Inv. Sy nc M1,2,3 (EOC) 2B+D, M4 M U X 2B1Q Encoding Scrambler M5,6 except CRC M U X CRC Generation M4 2B+D M U X Control uframer.emf Figure 33 U2B1Q Framer - Data Flow Scheme Data Sheet 62 2001-03-30 PEF 81912/81913 Functional Description * (M-bit handling acc. to ETR080) M5,6 except CRC D E M U X U2B1Q-Deframer M1,2,3 (EOC) 2B1Q Decoding D E M U X CRC Check Descrambler Sync/Inv. Sync D E M U X M4 2B+D Control udeframer.emf Figure 34 U2B1Q Deframer - Data Flow Scheme 2.4.2 Maintenance Channel The last three symbols (6 bits) of each basic frame are used as M (Maintenance)channel for the exchange of operation and maintenance data between the network and the NT. Approved M-bit data is first processed and then reported to the C by interrupt requests. The verification method is programmed in the MFILT register (see Chapter 4.11.2). EOC-data is inserted into the U-frame at the positions M1, M2 and M3 (Table 15) thereby permitting the transmission of two complete EOC-messages (2x 12 bits) within one U-superframe (see Chapter 2.4.3). M4 bits are used to communicate status and maintenance functions between the transceivers. The meaning of a bit position is dependent upon the direction of transmission (upstream/downstream) and the operation mode (NT/LT). See Table 15 for the different meaning of the M4 bits. For details see Chapter 2.4.4. The M5 and M6 bits contain the FEBE bit and the CRC bits. For details see Chapter 2.4.6. 2.4.2.1 Reporting to the C Interface The maintenance channel information is exchanged with external devices via the appropriate registers. Received maintenance channel information is reported to the C by an interrupt. Data Sheet 63 2001-03-30 PEF 81912/81913 Functional Description 2.4.2.2 Access from the C Interface The maintenance data to be transmitted can be programmed by writing the internal EOCW/M4W/M56W registers. 2.4.2.3 Availability of Maintenance Channel Information Transmission of the Maintenance channel data is only possible if a superframe is transmitted and the M-bits are transparent (M-Bits are "normal" in Table 25). In other states all maintenance bits are clamped to high. Reception of the Maintenance channel data is enabled by the state machine in the following states: Table 16 Enabling the Maintenance Channel (Receive Direction) Synchronized1 Synchronized2 Wait for ACT Transparent Error S/T Pend. Deac. S/T Pend. Deac. U Analog Loop Back Reporting and execution of maintenance information is only sensible if the Q-SMINT(R)IX is synchronous. Filters are provided to avoid meaningless reporting. Reset values are applied to the maintenance bits before the state machine enters one of the states in Table 16. 2.4.2.4 M-Bit Register Access Timing Since the maintenance data must be put into and read from the U-frame in time there is the need for synchronization if M-Bit data is exchanged via the C-interface. Below the timing is given for the access to the M-Bit read and write registers. The write access timing is depicted in Figure 35. Timing references for a write access are the 6 ms and 12 ms interrupts which are accommodated in the ISTAU register. An active 6 ms interrupt signals that from this event there is a time frame of 3 basic frames duration (4.5 ms) for the write access to the EOCW register. The 12 ms interrupt serves as time reference for the write access to the M4W and M56W registers. From the point of time the 12 ms interrupt goes active there is a time window of 7 basic frames to overwrite the register values. The programmed data will be sent out with the next U-superframe. Data Sheet 64 2001-03-30 PEF 81912/81913 Functional Description Note that the point of time when the 6 ms and 12 ms interrupts are generated within basic frame #1 and #5 is not fixed and may vary. * read access to ISTAU clears 6ms interrupt 6ms Interrupt Frame No. #1 C write access time to EOCW max. 3 Base Frames (4.5ms) #4 #5 C write access time to EOCW 3 Base Frames (4.5ms) #8 #1 1. EOC read access to ISTAU clears 12ms interrupt 2. EOC 12ms Interrupt Frame No. #1 C write access time to M4W, M56W max. 7 Base Frames (10.5ms) #8 #1 wr_acs_timg_QSMINT.emf Figure 35 Write Access Timing The read access timing is illustrated in Figure 36. An interrupt source of the same name is associated with each read register (EOCR, M4R, M56R). An EOC interrupt indicates that the value of the EOCR register has been changed and updated. So do the M4 and M56 interrupts. Note that unlike the 6 ms and 12 ms interrupts the 'read' interrupts are only generated on change of the register value and do not occur periodically. The EOC, M4 and M56 interrupt bits are all accommodated in the ISTAU register. Data Sheet 65 2001-03-30 PEF 81912/81913 Functional Description * set active in frame #1 or #5 if value has been updated read access to ISTAU clears EOC interrupt EOC Interrupt Frame No. #1 C read access time to EOCR max. 3 Base Frames (4.5ms) #4 #5 C read access time to EOCR 3 Base Frames (4.5ms) #8 #1 1. EOC set active in frame #1 if value has been updated read access to ISTAU clears M4 interrupt 2. EOC M4 Interrupt Frame No. #1 C read access time to M4R max. 7 Base Frames (10.5ms) set active in frame #1 if value has been updated read access to ISTAU clears M56 interrupt #8 #1 M56 Interrupt Frame No. #1 C read access time to M56R max. 7 Base Frames (10.5ms) #8 #1 wr_acs_timg_QSMINT.emf Figure 36 Read Access Timing 2.4.3 2.4.3.1 Processing of the EOC EOC Commands The EOC command consists of an address field, a data/message indicator and an eightbit information field. With the address field the destination of the transmitted message/ data is defined. Addresses are defined for the NT, 6 repeater stations and broadcasting. Data Sheet 66 2001-03-30 PEF 81912/81913 Functional Description The data/message indicator needs to be set to (1) to indicate that the information field contains a message. If set to (0), numerical data is transferred to the NT. Currently no numerical data transfer to or from the NT is required. * Table 17 EOC Address Field a1a2a3 000 111 0 01 1 10 Coding of EOC-Commands Data/ Information Message Indicator d/m x x x 0 1 1 1 1 1 1 1 1 1 01010000 01010001 01010010 01010011 01010100 11111111 00000000 10101010 O O O O O O D/O D D D D D D D O/D O i1 i2 i3 i4 i5 i6 i7 i8 Message O (rigin) D (estination) LT NT NT Broadcast Repeater stations No. 1 - No. 6 Data Message LBBD LB1 LB2 RCC NCC RTN H UTC * Table 18 Hexcode i1-i8 00 50 D H LBBD Usage of Supported EOC-Commands Function U H Hold. Provokes no change. The device issues Hold if no NT or broadcast address is used or if the d/m indicator is set to (0). Close complete loop-back (B1, B2, D). If this command is detected in NT EOC auto mode the C/I-code ARL is issued by the Q-SMINT(R)IX U-transceiver. 67 2001-03-30 Data Sheet PEF 81912/81913 Functional Description Table 18 Hexcode i1-i8 51 D LB1 U Closes B1 loop-back in NT. All B1-channel data will be looped back within the Q-SMINT(R)IX U-transceiver. The bits LB1 and U/IOM(R) are set in the register LOOP. Closes B2 loop-back in NT. All B2-channel data will be looped back within the Q-SMINT(R)IX U-transceiver. The bits LB2 and U/IOM(R) are set in the register LOOP. Request corrupt CRC. Upon receipt the Q-SMINT(R)IX transmits corrupted (= inverted) CRCs upstream. This allows to test the near end block error counter on the LT-side. The far end block error counter at the Q-SMINT(R)IX-side is stopped and Q-SMINT(R)IX-error indications are retained. Notify of corrupt CRC. Upon receipt of NCC the QSMINT(R)IX-block error counters (near-end only) are disabled and error indications are retained. This prevents wrong error counts while corrupted CRCs are sent. UTC Unable to comply. Message sent instead of an acknowledgment if an undefined EOC-command or d/m bit=0 was received by the Q-SMINT(R)IX. RTN Return to normal. With this command all previously sent EOC-commands will be released. The EOCW register is reset to its initial state (FFH). ACK Acknowledge. If a defined and correctly addressed EOCcommand was received by the Q-SMINT(R)IX, the Q-SMINT(R)IX replies by echoing back the received command. Usage of Supported EOC-Commands(cont'd) Function 52 LB2 53 RCC 54 NCC AA FF XX 2.4.3.2 EOC Processor The on-chip EOC-processor is responsible for the correct insertion and extraction of EOC-data on the U-interface. The EOC-processor can be programmed either to auto mode or to transparent modes (see Chapter 2.4.3.3). Figure 37 shows the registers and pins that are involved when EOC data is transmitted and received. Data Sheet 68 2001-03-30 PEF 81912/81913 Functional Description * U Receive Superframe MFILT.EOC EOCR Register EOC Message Filtering Last Verified EOC Message EOC Processor Echo Interrupt Controller INT eoc_rx.emf Figure 37 * EOC Message Reception U-Rx Frame EOC Processor C Enable EOC AUTO= '1' EOCW EOC Command/ Message every 6 msec U Transmit Superframe eoc_tx.emf Figure 38 EOC Command/Message Transmission Data Sheet 69 2001-03-30 PEF 81912/81913 Functional Description 2.4.3.3 EOC Operating Modes The EOC operating modes are programmable in the MFILT register (see Chapter 4.11.2) EOC Auto Mode - Acknowledgement: All received EOC-frames are echoed back to the exchange immediately without triple-last-look. If an address other than (000)B or (111)B is received, a HOLD message with address (000)B is returned. However there is an exception: The Q-SMINT(R)IX will send a 'UTC' after three consecutive receptions of d/ m = 0 or after an undefined command. - Latching: All detected EOC-commands, i.e. LBBD, RCC etc., are latched. Multiple subsequent valid EOC-commands are executed in parallel, as long as they are not disabled with the EOC 'RTN' command or a deactivation. - Reporting: With the triple-last-look criterion fulfilled the new EOC-command will be reported by an interrupt, independently of the address used and the status of the d/m indicator. The triple last look criterion implies that the new verified message is different to the last TLL-verified message. - Execution: The EOC-commands listed in Table 17 will be executed automatically by the U-transceiver if they were addressed correctly (000B or 111B) and the d/m bit was set to message (1). The execution of a command is performed only after the "triplelast-look" criterion is met. EOC Transparent Mode 6 ms - Acknowledgement: There is no automatic acknowledgement in transparent mode. Therefore the external C has to perform the EOC-Procedure. 2 msec must be available for the report and the subsequent access of the transmit EOC data of the next outgoing EOC-frame. - Latching: No latching is performed due to no execution. - Reporting: The received EOC-frame is reported to the C by an interrupt every 6 ms. Verification, acknowledgment and execution of the received command have to be initiated by an external controller. The C can program back all defined test functions (close/open loops, send corrupted CRCs). In the transmit direction, the last written EOC-code from the C is used. - Execution: No automatic execution in transparent modes. The appropriate actions can be programmed by the C. Transparent mode with 'On Change bit' active - Acknowledgment: There is no automatic acknowledgement in transparent mode. For details see above. - Latching: No latching is performed due to no execution. Data Sheet 70 2001-03-30 PEF 81912/81913 Functional Description - Reporting: This mode is almost identical to the Transparent Mode 6 ms. But a report to the C by an interrupt takes place only, if a change in the EOC message has been detected. - Execution: No automatic execution in transparent modes. The appropriate actions can be programmed by the C. Transparent mode with TLL active - Acknowledgement: There is no automatic acknowledgment in transparent mode. For details see above. - Latching: No latching is performed due to no execution. - Reporting: This mode is almost identical to the Transparent Mode 6 ms. But a report to the C by an interrupt takes place only, if the new EOC command has been detected in at least three consecutive EOC messages. - Execution: No automatic execution in transparent modes. The appropriate actions can be programmed by the C. 2.4.3.4 General Examples for different EOC modes In the following examples some letters like A,B,C are used to symbolize EOC command. There are also particular EOC commands mentioned which indicate special system behavior (e.g. UTC, H). The examples are shown in tables. Data Sheet 71 2001-03-30 PEF 81912/81913 Functional Description EOC Automode Table 19 remarks EOC Auto Mode NO report to system interface undef. command or d/m=0 UTC UTC input from C EOC TX EOC RX report to C Access to EOCW register has direct impact on EOC TX. AAABAAAHHHDD ADD UTC D AAABAAACCCDDDDADDD A C D * A, B: EOC commands with correct address, d/m bit = 1 and defined command. * C: EOC command with wrong address. Immediately acknowledged with H. * D: EOC command which is not defined or d/m bit = 0. Acknowledgement after TLL with UTC. Data Sheet 72 wrong address -> H immediately akcn. immediately akcn. 2001-03-30 PEF 81912/81913 Functional Description Transparent mode 6 ms) Table 20 remarks input from C EOC TX EOC RX report to C A A C C A A A A B B A C C B B C C B A A B A A C C A A C A A C B B D D B B D B B D B B Transparent mode 6 ms Transparent mode '@change' Table 21 remarks input from C EOC TX EOC RX report to C Transparent mode TLL Table 22 remarks saturation Transparent mode TLL single EOC 'B' interrupts TLL saturnation D A B 2001-03-30 Transparent mode '@change' A A C A A A A B B A C C B B C B A A B A C C A C A C A C B B D D B D B input from C EOC TX EOC RX report to C A A B C AAABBBBBCCCCDDDD C A CCCCCAAABAAABBBBB Data Sheet 73 PEF 81912/81913 Functional Description 2.4.4 2.4.4.1 Processing of the Overhead Bits M4, M5, M6 M4 Bit Reporting to the C Four different validation modes can be selected and take effect on a per bit base. Only if the received M4 bit change has been approved by the programmed filter algorithm a report to the C is triggered. The following filter algorithms are provided and can be programmed in the MFILT register: * On Change * Triple-Last-Look (TLL) coverage * CRC coverage Note that unlike the M4 bits the M56 bits are not included in the CRC generation! * CRC and TLL coverage 2.4.4.2 M4 Bit Reporting to State Machine Some M4 bits, ACT, DEA and UOA, have two destinations, the state machine and the C. Regarding these bits Triple-Last-Look (TLL) is applied by default before the changed status is input to the state machine. Via the MFILT register the user can decide whether the M4 bits which are input to the state machine shall be approved * by TLL (default setting, since TLL is a Bellcore requirement) or * by the same verification mode as selected for reporting to the C. The reset values before activation are ACT=0, DEA=1, UOA=0. 2.4.4.3 M5, M6 Bit Reporting to the C By default changes in the received spare bits M51, M52, and M61 are reported to the C only if no CRC violation has been detected. However the user has the choice to program one of the following two options in the MFILT register (for details see Chapter 4.11.2): * Same validation algorithm is applied to M5 and M6 bits as programmed for M4 bits * On Change In transmit direction these bits are set by default to '1' if they are not explicitly set by an C access (via M56W register). 2.4.4.4 Summary of M4, M5, M6 Bit Reporting Figure 39 summarizes again the various filtering options that are provided for the several maintenance channel bits. Data Sheet 74 2001-03-30 PEF 81912/81913 Functional Description * MFILT.EOC(Bit3,2,1) M U X State Machine TLL M4 CRC On Change & M U X MFILT.M4(Bit5) M4 INT MFILT.M4(Bit4,3) TLL M5, M6 CRC On Change & M U X M U X M56 INT MFILT.M56(Bit6) m456_filter_QSMINT.emf Figure 39 Maintenance Channel Filtering Options Figure 40 illustrates the point of time when a detected M4, M5, M6 bit change is reported to the C and when it is reported to the state machine: * towards the C reports are always sent after one complete U-superframe was received, * whereas towards the state machine M4-bit changes (ACT, DEA, UOA, SAI) are instantly passed on as soon as they were approved. In context of Figure 40 this means that a verified ACT bit change is already reported at the end of basic frame #1 instead of the end of basic frame #8. * n. Super Frame 1. Basic Frame ISW 2B+D M1-6 SW 2. Basic Frame 2B+D M1-6 SW 8. Basic Frame 2B+D M1-6 n+1. Super Frame ISW 2B+D M1-6 M4= ACT Time e.g. ACT bit validated INT reported to State Machine m4tim2sm_QSMINT.emf Figure 40 Data Sheet M4 Bit Report Timing (Statemachine vs. C) 75 2001-03-30 PEF 81912/81913 Functional Description However, if the same filter is selected towards the state machine as programmed towards the C, the user has to be aware that if CRC mode is active, the state machine is informed at the end of the next U-superframe. 2.4.5 M4, M5, M6 Bit Control Mechanisms Figure 41 and Figure 42 show the control mechanisms that are provided for M4, M5 and M6 bit data: Via the M4WMASK register the user can selectively program which M4 bits are externally controlled and which are set by the internal state machine or dedicated pins (PS1, PS2). If one M4WMASK bit is set to '0' then the M4 bit value in the U-transmit frame is determined by the bit value at the corresponding bit position in the M4W register. Note: By bit 6 in the M4WMASK register it can be selected whether SAI is set by the state machine or by C access and whether the value of the received UOA bit is reported to the state machine or UOA= '1' is signalled. Via the M4RMASK register the user can selectively program which M4 bit changes shall cause an report to the C. The M4W register latches the M4 bits that are sent with the next available U-superframe. The M4R register contains the last validated M4 bit data. The default value of M51, M52 and M61 can be overwritten at any time by use of register M56W. M56R latches the last received and verified M5, M6 bit data. The control of the FEBE bit is performed by the CRC-Processor, see Chapter 2.4.6. Data Sheet 76 2001-03-30 PEF 81912/81913 Functional Description * U Receive Superframe MFILT.M4 M4 Filtering (per bit) MFILT.M56 M56 Filtering (per bit) M4R Register UOA DEA ACT AIB UOA M46 M45 M44 SCO DEA ACT M56R Register 0 MS2 MS1 NEBE M61 M52 M51 FEBE EN/ DIS EN/ DIS EN/ DIS EN/ DIS EN/ DIS EN/ DIS EN/ DIS EN/ DIS M4RMASK '0'= enabled '1'= disabled '1' M4WMASK.Bit6 MUX UOA DEA ACT Interrupt Controller State Machine INT m456_nt_rx_QSMINT.e Figure 41 * M4, M5, M6 Bit Control in Receive Direction Pins PS2 PS1 C/I Codes C M4W Register NIB SAI M46 CSO NTM PS2 PS1 ACT SAI State Machine ACT MUX m456_nt_tx_QSMINT.emf '1' '1' '0' '1' M4WMASK '1'= M4W Reg. '0'= SM/ Pin MUX MUX MUX MUX MUX MUX M4WMASK.Bit6 MUX U Transmit Superframe MUX OPMODE.FEBE M56W Register 1 1 1 1 M61 M52 M51 FEBE NEBE Counter C Figure 42 M4, M5, M6 Bit Control in Transmit Direction Data Sheet 77 2001-03-30 PEF 81912/81913 Functional Description 2.4.6 Cyclic Redundancy Check / FEBE bit An error monitoring function is implemented covering the 2B + D and M4 data transmission of a U-superframe by a Cyclic Redundancy Check (CRC). The computed polynomial is: G (u) = u12 + u11 + u3 + u2 + u + 1 (+ modulo 2 addition) The check digits (CRC bits CRC1, CRC2, ..., CRC12) generated are transmitted in the U-superframe. The receiver will compute the CRC of the received 2B + D and M4 data and compare it with the received CRC-bits generated by the transmitter. A CRC-error will be indicated to both sides of the U-interface, as a NEBE (Near-end Block Error) on the side where the error is detected, as a FEBE (Far-end Block Error) on the remote side. The FEBE-bit will be placed in the next available U-superframe transmitted to the originator. Figure 43 illustrates the CRC-process. Data Sheet 78 2001-03-30 PEF 81912/81913 Functional Description * IOM(R)-2 NT (2B + D), M4 U SFR(n) LT IOM(R)-2 DD G(u) G(u) DD CRC1... CRC12 CRC1... CRC12 No SFR(n + 1) =? Yes CRCOK=1 SFR(n + 1.0625)* CRCOK=0 INT C access NEBE Error Counter FEBE = "1" SFR(n + 1.0625) FEBE = "0" FEBE Error Counter (MON-8) DU G(u) SFR(n + 0.0625) (2B + D), M4 DU G(u) CRC 1... CRC 12 CRC 1... CRC 12 SFR(n + 1.0625) =? No Yes C access INT FEBE Error Counter SFR(n + 2) FEBE = "1" SFR(n + 2) FEBE = "0" CRCOK=1 CRCOK=0 NEBE Error Counter (MON-8) *0.0625 of a SFR is the 60 Quats offset of the NT transmit data. crc_QSMINT.emf Figure 43 Data Sheet CRC-Process 79 2001-03-30 PEF 81912/81913 Functional Description 2.4.7 Block Error Counters The U-transceiver provides internal counters for far-end and near-end block errors. This allows a comfortable surveillance of the transmission quality at the U-interface. In addition, the occurrence of near-end errors, far-end errors, and the simultaneous occurrence of both errors are reported to the C by an interrupt at the beginning of the following receive-superframe. A block error is detected each time when the calculated checksum (CRC) of the received data does not correspond to the control checksum transmitted in the successive superframe. One block error thus indicates that one U-superframe has not been transmitted correctly. No conclusion with respect to the number of bit errors is therefore possible. 2.4.7.1 Near-End and Far-End Block Error Counter A near-end block error (NEBE) indicates that the error has been detected in the receive direction (i.e. NEBE in the NT = LT => NT error). Each detected NEBE-error increments the 8-bit NEBE-counter. When reaching the maximum count, counting is stopped and the counter value reads (FFH). A far-end block error identifies errors in transmission direction (i.e. FEBE in the NT = NT => LT-error). FEBE errors are processed in the same manner as NEBE-errors. The FEBE and NEBE counter values can be read in registers FEBE and NEBE. The counter is cleared after read. The counters are also reset to 00H in all states except the states listed in Table 16. 2.4.7.2 Testing Block Error Counters Figure 44 illustrates how near- and far-end block error counters can be tested. Transmission errors are simulated with artificially corrupted CRCs. With two commands the cyclic redundancy checksum can be inverted in the upstream and downstream direction. A third command offers to invert single FEBE-bits. * EOC Command NCC: Requests the Q-SMINT(R)IX to notify corrupted CRCs. The functional behavior of the Q-SMINT(R)IX and the NEBE-counter depends on the mode selected: - EOC auto mode: NEBE-detection stopped: no NEBE interrupt generated and NEBE-counter disabled - EOC transparent mode NEBE-detection enabled: NEBE interrupt generated and NEBE-counter enabled * EOC Command RCC: Requests the Q-SMINT(R)IX to send corrupt CRCs. After issuing RCC near-end block errors will be registered on the LT-side. Data Sheet 80 2001-03-30 PEF 81912/81913 Functional Description The functional behavior of the Q-SMINT(R)IX and the FEBE-counter depends on the mode selected: EOC auto mode: The Q-SMINT(R)IX will react with a permanently inverted upstream CRC. FEBE-detection stopped: no FEBE interrupt generated and FEBE-counter disabled EOC transparent mode The external C must react on RCC by programming TEST.CCRC = '1'. FEBE-detection enabled: FEBE interrupt generated and FEBE-counter enabled EOC command RTN: Disables all previously sent EOC commands. M56W.FEBE By setting / resetting M56W.FEBE (M56W.FEBE can only be set and controlled externally if OPMODE.FEBE is set to '1'), the FEBE bit of the next available U-frame can be set / reset . Therefore, it is possible to predict exactly the FEBE-counter value. - - * * Data Sheet 81 2001-03-30 PEF 81912/81913 Functional Description * C Interface ISTAU.EOC=1 EOCR = 'NCC' EOC Transparent EOC Auto-Mode U LT IOM(R) -2 STOP ERROR DETECT ERROR COUNT NEBE EOC : NCC EOC Acknowledge Start Inverse CRC Bits FEBE = "0" ERROR COUNT FEBE End Inverse CRC Bits (MON-0) NCC (MON-0) ACK (MON-8) CCRC (MON-8) RBEF (MON-8) ABEC (MON-8) NORM (MON-0) RTN (MON-0) ACK ISTAU.FEBE/ NEBE=1 M56R.NEBE = '1' ISTAU.EOC=1 EOCR = 'RTN' FREE ERROR DETECT EOC : RTN EOC Acknowledge ISTAU.EOC=1 EOCR = 'RCC' STOP ERROR DETECT EOC : RCC EOC Acknowledge Start Inverse CRC Bits (MON-0) RCC (MON-0) ACK TEST.CCRC = '1' ISTAU.FEBE/ NEBE=1 M56R.FEBE = '1' ERROR COUNT FEBE FEBE = "0" ERROR COUNT NEBE EOC : RTN FREE ERROR DETECT EOC Acknowledge End Inverse CRC Bits (MON-8) RBEN (MON-8) ABEC (MON-0) RTN ISTAU.EOC=1 EOCR = 'RTN' TEST.CCRC = '0' ITD04226_QSMINT.emf Figure 44 Block Error Counter Test 2.4.8 Scrambling/ Descrambling The scrambling algorithm ensures that no sequences of permanent binary 0s or 1s are transmitted. The scrambling / descrambling process is controlled fully by the QSMINT(R)IX . Hence, no influence can be taken by the user. 2.4.9 C/I Codes The operational status of the U-transceiver is controlled by the Control/Indicate channel (C/I-channel). Data Sheet 82 2001-03-30 PEF 81912/81913 Functional Description Table 23 presents all defined C/I codes. A new command or indication will be recognized as valid after it has been detected in two successive IOM(R)-2-frames (double last-look criterion). Note: Unconditional C/I-Commands must be applied for at least 4 IOM(R)-2 frames for reliable recognition by the U-transceiver. Commands have to be applied continuously on DU until the command is validated by the U-transceiver and the desired action has been initiated. Afterwards the command may be changed. An indication is issued permanently by the U-transceiver on DD until a new indication needs to be forwarded. Because a number of states issue identical indications it is not possible to identify every state individually. * Table 23 Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 U - Transceiver C/I Codes IN TIM RES - - EI1 SSP DT - AR - ARL - AI - - DI OUT DR - - - EI1 - - PU AR - ARL - AI - AIL DC AI: Activation Indication AIL: Activation Indication Loop AR: Activation Request ARL: Activation Request Local Loop Data Sheet 83 2001-03-30 PEF 81912/81913 Functional Description DC: Deactivation Confirmation DI: Deactivation Indication DR: Deactivation Request DT: Data Through test mode EI1: Error Indication 1 PU: Power-Up RES: Reset SSP: Send Single Pulses test mode TIM: Timing request 2.4.10 State Machines for Line Activation / Deactivation 2.4.10.1 Notation The state machines control the sequence of signals at the U-interface that are generated during the start-up procedure. The informations contained in the following state diagrams are: - - - - - - * State name U-signal transmitted Overhead bits transmitted C/I-code transmitted Transition criteria Timers Figure 45 shows how to interpret the state diagrams. IN Signal Transmitted to U-Interface (general) State Name Single Bit Transmitted to U-Interface Indication Transmitted on C/I-Channel (DOUT) ITD04257.vsd OUT Figure 45 Data Sheet Explanation of State Diagram Notation 84 2001-03-30 PEF 81912/81913 Functional Description Combinations of transition criteria are possible. Logical "AND" is indicated by "&" (TN & DC), logical "OR" is written "or" and for a negation "/" is used. The start of a timer is indicated with "TxS" ("x" being equivalent to the timer number). Timers are always started when entering the new state. The action resulting after a timer has expired is indicated by the path labelled "TxE". Data Sheet 85 2001-03-30 PEF 81912/81913 Functional Description 2.4.10.2 Standard NT State Machine (IEC-Q / NTC-Q Compatible) * T14S SN0 . T14E T14S TL Pending Timing DC Any State SSP or C/I= 'SSP' T14S DI . SN0 Deactivated DC TIM DI AR or TL SP Test DR . . SN0 IOM Awaked PU AR or TL SN0 Reset Any State Pin-RST or C/I= 'RES' DR ARL . DI DI & NT-AUTO T1S, T11S TN DC . Alerting PU T12S T1S T11S . TN Alerting 1 DR T11E T12S T1S, T11S T11E T12S SN1 . EC-Training AL DC LSEC or T12E LSUE or T1E . SN1 EC-Training DC SN0 SN1 DI . EC-Training 1 DR LSEC or T12E act=0 SN3 Wait for SF AL DC BBD1 & SFD .. BBD0 & FD EQ-Training DC T20S SN3T act=0 Analog Loop Back AR LSUE or T1E SN2 . T20E & BBD0 & SFD LOF Wait for SF DC DI SN3/SN3T act=1/0 Pend.Deact. S/T DR LSUE 1) 3) dea=0 LOF SN3/SN3T act=0 Synchronized 1 DC uoa=1 1) dea=0 LSUE uoa=0 dea=0 LSUE LOF SN3/SN3T 1) act=0 Synchronized 2 2) AR/ARL Al LOF SN3/SN3T 1) act=1 Wait for Act 2) El1 AR/ARL act=1 act=0 uoa=0 dea=0 LSUE Any State DT or C/I='DT' LOF El1 act=1 SN3T Transparent 2) AI/AIL act=1 & Al uoa=0 dea=0 LSUE Yes SN3/SN3T 1) act=0 Error S/T act=0 2) AR/ARL dea=0 uoa=0 LSUE uoa=1 ? No dea=1 LOF . SN0 Pend Receive Res. T13S EI1 LSU or ( /LOF & T13E ) T7S LOF SN3/SN3T act=1/0 3) Pend.Deact. U DC LSU 1) T7E & DI . SN0 Receive Reset DR T7S TL Figure 46 Standard NT State Machine (IEC-Q / NTC-Q Compatible) (Footnotes: see "Dependence of Outputs" on Page 91) 86 2001-03-30 Data Sheet PEF 81912/81913 Functional Description Note: The test modes `Data Through` (DT) and `Send Single Pulses` (SSP) are invoked via C/I codes 'DT' and 'SSP' according to Table 23. Setting SRES.RES_U to `1` forces the U-transceiver into test mode `Quiet Mode` (QM), i.e. the U-transceiver is hardware reset. If the Metallic Loop Termination is used, then the U-transceiver is forced into the states `Reset` and `Transparent` by valid pulse streams on pin MTI according to Table 30. Note: If the state machine is in state 'Deactivated' and the IOM(R)-2 clocks are not running, then the transitions to 'IOM(R)-2 Awaked' or 'Alerting' can be invoked by writing directly the corresponding C/I-code to register UCIW via the C interface. 2.4.10.3 Inputs to the U-Transceiver: C/I-Commands: AI Activation Indication The downstream device issues this indication to announce that its layer-1 is available. The U-transceiver informs the LT side by setting the "ACT" bit to "1". Activation Request The U-transceiver is requested to start the activation process by sending the wakeup signal TN. Activation Request Local Loop-back The U-transceiver is requested to operate an analog loop-back (close to the Uinterface) and to begin the start-up sequence by sending SN1 (without starting timer T1). This command may be issued only after the U-transceiver has been HW- or SWreset. This eases that the EC- and EQ-coefficient updating algorithms converge correctly. The ARL-command has to be issued continuously as long as the loop-back is required. Deactivation Indication This indication is used during a deactivation procedure to inform the U-transceiver that it may enter the deactivated (power-down) state. Data Through This unconditional command is used for test purposes only and forces the Utransceiver into the "Transparent" state. Error Indication 1 The downstream device indicates an error condition (loss of frame alignment or loss of incoming signal). The U-transceiver informs the LT-side by setting the ACT-bit to "0" thus indicating that transparency has been lost. Reset Unconditional command which resets the U-transceiver. Send Single Pulses Unconditional command which requests the transmission of single pulses on the U-interface. AR ARL DI DT EI1 RES SSP Data Sheet 87 2001-03-30 PEF 81912/81913 Functional Description TIM Timing The U-transceiver is requested to enter state 'IOM(R)-2 Awaked'. U-Interface Events: ACT = 0/1 ACT-bit received from LT-side. - ACT = 1 requests the U-transceiver to transmit transparently in both directions. In the case of loop-backs, however, transparency in both directions of transmission is established when the receiver is synchronized. - ACT = 0 indicates that layer-2 functionality is not available. DEA = 0/1 DEA-bit received from the LT-side - DEA = 0 informs the U-transceiver that a deactivation procedure has been started by the LT-side. - DEA = 1 reflects the case when DEA = 0 was detected by faults due to e.g. transmission errors and allows the U-transceiver to recover from this situation. UOA = 0/1 UOA-bit received from network side - UOA = 0 informs the U-transceiver that only the U-interface is to be activated. The S/T-interface must be deactivated. - UOA = 1 requests the S/T-interface (if present) to activate. Timers The start of timers is indicated by TxS, the expiry by TxE. Table 24 shows which timers are used: * Table 24 Timer T1 T7 T11 T12 T13 T14 T20 Timers Used Duration (ms) 15000 40 9 5500 15000 0.5 10 Function Supervisor for start-up Hold time TN-transmission Supervisor EC-converge Frame synchronization Hold time Hold time Receive reset Alerting EC-training Pend. receive reset Pend. timing Wait for SF State 2.4.10.4 Outputs of the U-Transceiver: The following signals and indications are issued on IOM(R)-2 (C/I-indications) and on the U-interface (predefined U-signals): Data Sheet 88 2001-03-30 PEF 81912/81913 Functional Description C/I-Indications AI Activation Indication The U-transceiver has established transparency of transmission. The downstream device is requested to establish layer-1 functionality. Activation Indication Loopback The U-transceiver has established transparency of transmission. The downstream device is requested to establish a loopback #2. Activation Request The downstream device is requested to start the activation procedure. Activation Request Loop-back The U-transceiver has detected a loop-back 2 command in the EOC-channel and has established transparency of transmission in the direction IOM(R)-2 to U-interface. The downstream device is requested to start the activation procedure and to establish a loopback #2. Deactivation Confirmation Idle code on the IOM(R)-2-interface. Deactivation Request The U-transceiver has detected a deactivation request command from the LT-side for a complete deactivation or a S/T only deactivation. The downstream device is requested to start the deactivation procedure. Error Indication 1 The U-transceiver has entered a failure condition caused by loss of framing on the U-interface or expiry of timer T1. AIL AR ARL DC DR EI1 Signals on U-Interface The signals SNx, TN and SP transmitted on the U-interface are defined in Table 25. * Table 25 Signal TN 1) SN0 SN1 SN2 SN3 SN3T Test Mode SP 2) U-Interface Signals Synch. Word (SW) 3 no signal present present present present test signal Superframe (ISW) 3 no signal absent absent present present test signal 2B + D 3 no signal 1 1 1 normal test signal M-Bits 3 no signal 1 1 normal normal test signal Data Sheet 89 2001-03-30 PEF 81912/81913 Functional Description Note: Note: 1)Alternating 2) 4 3 symbols at 10 kHz. Options for the test signal can be selected by register TEST: A 40 kHz signal composed by alternating +/-3 or +/-1 transmit pulses. A series of single pulses spaced at intervals of 1.5 ms; Either alternating +/-1 or +/-3 pulses can be selected. Input Signals of the State Machine and related U-Signals The table below summarizes the input signals that control the NT state machine and that are extracted from the U-interface signal sequences. * LOF LSEC LSU Loss of framing This condition is fulfilled if framing is lost for 573 ms. Loss of signal behind echo canceller Internal Signal which indicates that the echo canceller has converged Loss of Signal on U-Interface This signal indicates that a loss of signal level for a duration of 3 ms has been detected on the U-interface. This short response time is relevant in all cases where the NT waits for a response (no signal level) from the LTside. Loss of Signal on U-Interface - Error condition After a loss of signal has been noticed, a 588 ms timer is started. When it has elapsed , the LSUE-criterion is fulfilled. This long response time (see also LSU) is valid in all cases where the NT is not prepared to lose signal level i.e. the LT has stopped transmission because of loss of framing, an unsuccessful activation, or the transmission line is interrupted. Frame Detected Super Frame Detected BBD0/1 Detected These signals are set if either '1' (BBD1) or '0' (BBD0) were detected in 4 subsequent basic frames. It is used as a criterion that the receiver has acquired frame synchronization and both its EC- and EQ-coefficients have converged. BBD0 corresponds to the received signal SL2 in case of a normal activation, BBD1 corresponds to the internally received signal SN3 in case of analog loop back. Awake tone detected The U-transceiver is requested to start an activation procedure. LSUE FD SFD BBD0 / BBD1 TL Data Sheet 90 2001-03-30 PEF 81912/81913 Functional Description Signals on IOM(R)-2 The Data (B+B+D) is set to all '1's in all states besides the states listed in Table 16. Dependence of Outputs * Outputs denoted with 1) in Figure 46: Signal output on Uk0 depends on the received EOC command and on the history of the state machine according to Table 26: * Table 26 Signal Output on Uk0 History of the State Machine no influence Signal output on Uk0 SN3T SN3 EOC Command received 'LBBD' received no 'LBBD' or 'RTN' state 'Transparent' has not been after an 'LBBD' reached previously during this activation procedure state 'Transparent' has been reached previously during this activation procedure SN3T * Outputs denoted with 2) in Figure 46: C/I-code output depends on received EOC-command 'LBBD' according to Table 27: * Table 27 C/I-Code Output Synchroni zed 2 AR ARL Wait for Act Transparent AR ARL AI AIL Error S/T AR ARL EOC Command received no 'LBBD' or 'RTN' after an 'LBBD' received 'LBBD' * Outputs denoted with 3) in Figure 46: In States 'Pend. Deact. S/T' and 'Pend. Deact. U' the ACT-bit output depends on its value in the previous state. * The value of the issued SAI-bit depends on the received C/I-code: DI and TIM lead to SAI = 0, any other C/I-code sets the SAI-bit to 1 indicating activity of the downstream device. * If state Alerting is entered from state Deactivated, then C/I-code 'PU' is issued, else C/I-code 'DC' is issued. Data Sheet 91 2001-03-30 PEF 81912/81913 Functional Description 2.4.10.5 Description of the NT-States The following states are used: Alerting The wake-up signal TN is transmitted for a period of T11 either in response to a received wake-up signal TL or to start an activation procedure on the LT-side. Alerting 1 "Alerting 1" state is entered when a wake-up tone was received in the "Receive Reset" state and the deactivation procedure on the NT-side was not yet finished. The transmission of wake-up tone TN is started. Analog Loop-Back Transparency is achieved in both directions of transmission. This state can be left by making use of any unconditional command. Deactivated Only in state Deactivated the device may enter the power-down mode. EC Training The signal SN1 is transmitted on the U-interface to allow the NT-receiver to update the EC-coefficients. The automatic gain control (AGC), the timing recovery and the EQ updating algorithm are disabled. EC-Training 1 The "EC-Training 1" state is entered if transmission of signal SN1 has to be started and the deactivation procedure on the NT-side is not yet finished. EC-Training AL The signal SN1 is transmitted on the U-interface to allow the NT-receiver to update the EC-coefficients. The automatic gain control (AGC), the timing recovery and the EQ updating algorithm are disabled. EQ-Training The receiver waits for signal SL1 or SL2 to be able to update the AGC, to recover the timing phase, to detect the synch-word (SW), and to update the EQ-coefficients. Data Sheet 92 2001-03-30 PEF 81912/81913 Functional Description Error S/T The downstream device is in an error condition (EI1). The LT-side is informed by setting the ACT-bit to "0" (loss of transparency on the NT-side). IOM(R)-2-Awaked The U-transceiver is deactivated, but may not enter the power-down mode. Pending Deactivation of S/T The U-transceiver has received the UOA-bit at zero after a complete activation of the S/ T-interface. The U-transceiver requests the downstream device to deactivate by issuing DR. Pending Deactivation of U-Interface The U-transceiver waits for the receive signal level to be turned off (LSU) to start the deactivation procedure. Pending Receive Reset The "Pending Receive Reset" state is entered upon detection of loss of framing on the U-interface or expiry of timer T1. This failure condition is signalled to the LT-side by turning off the transmit level (SN0). The U-transceiver then waits for a response (no signal level LSU) from the LT-side. Pending Timing In the NT-mode the pending timing state assures that the C/I-channel code DC is issued four times before entering the 'Deactivated' state. Receive Reset In state 'Receive Reset' a reset of the Uk0-receiver is performed, except in case that state 'Receive Reset' was entered from state 'Pend. Deact. U'. Timer T7 assures that no activation procedure is started from the NT-side for a minimum period of time of T7. This gives the LT a chance to activate the NT. Reset In state 'Reset' a software-reset is performed. Synchronized 1 State 'Synchronized 1' is the fully active state of the U-transceiver, while the downstream device is deactivated. Data Sheet 93 2001-03-30 PEF 81912/81913 Functional Description Synchronized 2 In this state the U-transceiver has received UOA = 1. This is a request to activate the downstream device. Test The test signal SP is issued as long as C/I=SSP is applied. For further details see Table 25. Transparent This state is entered upon the detection of ACT = 1 received from the LT-side and corresponds to the fully active state. Wait for ACT Upon the receipt of AI, the NT waits for a response (ACT = 1) from the LT-side. Wait for SF The signal SN2 is sent on the U-interface and the receiver waits for detection of the superframe. Wait for SF AL This state is entered in the case of an analog loop-back and allows the receiver to update the AGC, to recover the timing phase, and to update the EQ-coefficients. 2.4.10.6 Simplified NT State Machine As an alternative to the activation/deactivation state machine of the U-transceiver known from the IEC-Q [9], a more software friendly state machine can be selected. In the early days of ISDN, the activation and deactivation procedure in a NT was completely determined by the U- and S-transceiver state machines without a microcontroller being necessary. Intelligent NTs or U-terminals require a microcontroller and software. In this case the software controls both the S-and the U-transceiver state machine. The simplified U-transceiver state machine was developed to better address the needs and requirements of software running on the microcontroller. The simplified state machine offers the following advantages: - the software can tell whether the IOM(R)-2 clocks are active or powered down via the received C/I code - From the received C/I code the software always knows, what it is expected to do and what options it has. The software does not have to backtrack older C/I codes. Data Sheet 94 2001-03-30 PEF 81912/81913 Functional Description - unnecessary C/I changes at irrelevant state transitions are omitted, hence the number of interrupts is reduced. All advantages can be offered by the following minor changes to the existing state machine: * Table 28 Change Changes to achieve Simplified NT State Machine State Standard NT State Machine DC/PU DC DC DC DC EI1 DC DC DC no changes DI DI or TIM DI or TIM DI or TIM Simplified NT State Machine PU PU PU PU PU DR DR DR DR Change of Transmitted C/I -Code Alerting EC-Training EQ-Training Wait for SF Synchronized 1 Pend. Receive Res. Pend. Deact. U. Wait for SF AL EC-Training AL all other States Changed State Transition Criteria Alerting 1 to Alerting EC-Training 1 to DI EC-Training Pend. Deact. S/T DI to Synchron. 1 all other transition criterias New State Transitions Receive Reset to none IOM(R)-2 Awaked Reset to IOM(R)-2 none Awaked no changes T7E & TIM TIM Data Sheet 95 2001-03-30 PEF 81912/81913 Functional Description Table 28 Change Changes to achieve Simplified NT State Machine(cont'd) State Test to IOM(R)-2 Awaked Not Supported State Transitions Reset to Alerting DI & NTAUTO all other transitions no changes none Standard NT State Machine none Simplified NT State Machine TIM Data Sheet 96 2001-03-30 PEF 81912/81913 Functional Description * T14S SN0 . T14E T14S TL Pending Timing DC Any State SSP or C/I= 'SSP' T14S DI . SN0 Deactivated DC TIM DI AR or TL SP Test DR . TIM . SN0 IOM Awaked PU AR or TL SN0 Reset Any State Pin-RST or C/I= 'RES' DR ARL . DI T1S, T11S TN Alerting PU T11E . T1S T11S . TN Alerting 1 DR T11E T1S, T11S T12S SN1 . EC-Training AL DR LSEC or T12E LSUE or T1E . SN1 EC-Training PU SN0 T12S DI or TIM . SN1 EC-Training 1 DR T12S LSEC or T12E act=0 SN3 Wait for SF AL DR BBD1 & SFD .. BBD0 & FD EQ-Training PU T20S SN3T act=0 Analog Loop Back AR LSUE or T1E SN2 . T20E & BBD0 & SFD LOF Wait for SF PU DI or TIM dea=0 LSUE uoa=0 dea=0 LSUE SN3/SN3T 1) act=1/0 3) Pend.Deact. S/T DR LSUE dea=0 LOF SN3/SN3T 1) act=0 Synchronized 1 PU uoa=1 LOF SN3/SN3T 1) act=0 Synchronized 2 2) AR/ARL Al LOF SN3/SN3T 1) act=1 Wait for Act 2) El1 AR/ARL act=1 act=0 uoa=0 dea=0 LSUE Any State DT or C/I='DT' LOF El1 act=1 SN3T Transparent 2) AI/AIL act=1 & Al uoa=0 dea=0 LSUE Yes SN3/SN3T 1) act=0 Error S/T act=0 2) AR/ARL dea=0 uoa=0 LSUE uoa=1 ? No dea=1 LOF . SN0 Pend Receive Res. T13S DR LSU or ( /LOF & T13E ) T7E & TIM T7E & DI T7S LOF SN3/SN3T act=1/0 3) Pend.Deact. U DR LSU 1) . SN0 Receive Reset DR T7S TL Figure 47 Simplified NT State Machine Data Sheet 97 2001-03-30 PEF 81912/81913 Functional Description * Table 29 C/I ind. Appearance of the State Machine to the Software Meaning Options Utransp arent Acknowledge and give permission to turn off the clocks Acknowledge, clocks will stay active no DR LT has decided to deactivate or DI activation was lost: - after an activation or - after an activation attempt or TIM - after reset TIM four IOM(R)-2 frames with C/I code DC are issued before AR permission to turn off the clocks any other C/Icode clocks are on; U-interface is not transparent but may be synchronous (e.g. U-only activation) any C/Icode DC turn on clocks no start U-activation no action, permission to turn off the clocks will be given no action, clocks will remain on no PU AR used during activation. UAI interface is synchronous and is waiting for an ok from the downstream device U-interface transparent -EI1 or act=0 no accept that activation can continue, layer 2 of the downstream device is ready. Then wait for CI/ indication AI no action, transmit data yes report problem on downstream device AI 2.4.11 Metallic Loop Termination For North American applications a maintenance controller according to ANSI T1.601 section 6.5 is implemented. The maintenance pulse stream from the U-interface Metallic Loop Termination circuit (MLT) is fed to pin MTI, usually via an optocoupler. It is digitally filtered for 20 ms and decoded independently on the polarity by the maintenance controller according to Table 30. Therefore, the maintenance controller is capable of detecting the DC and AC signaling format. The Q-SMINT(R)IX automatically sets the Utransceiver in the proper state and issues an interrupt. The state selected by the MLT is indicated via two bits. The Q-SMINT(R)IX reacts on a valid pulse stream independently of the current Utransceiver state. This includes the power-down state. Data Sheet 98 2001-03-30 PEF 81912/81913 Functional Description A test mode is valid for 75 seconds. If during the 75 seconds a valid pulse sequence is detected the 75 s timer starts again. After expiry of the 75 s timer the MLT maintenance controller goes back to normal operation. * Table 30 ANSI Maintenance Controller States ANSI maintenance controller state ignored Quiet Mode ignored U-transceiver State Machine no impact transition to state 'Reset' start timer 75s no impact Number of counted pulses <= 5 6 7 8 9 10 >= 11 Insertion Loss Measurement transition to state 'Transparent' start timer 75s ignored normal operation ignored no impact transition to state 'Reset' no impact Figure 48 shows examples for pulse streams with inverse polarity selecting Quiet Mode. * 20 ms < tHIGH < 500 ms 4 ms < tLOW < 500 ms Pin 1 MTI 0 500 ms 1 2 3 4 5 6 500 ms 20 ms < tLOW < 500 ms 4 ms < tHIGH < 500 ms Pin 1 MTI 0 500 ms 1 2 3 4 5 6 500 ms mlt.vsd Figure 48 Pulse Streams Selecting Quiet Mode Data Sheet 99 2001-03-30 PEF 81912/81913 Functional Description 2.4.12 U-Transceiver Interrupt Structure The U-Interrupt Status register (ISTAU) contains the interrupt sources of the UTransceiver (Figure 49). Each source can be masked by setting the corresponding bit of the U-Interrupt Mask register (MASKU) to '1'. Such masked interrupt status bits are not indicated when ISTAU is read and do not generate an interrupt request. The ISTAU register is cleared on read access. The interrupt sources of the ISTAU register (UCIR, EOCR, M4R, M56R) need not be evaluated. When at time t1 an interrupt source generates an interrupt, all further interrupts are collected. Reading the ISTAU register clears all interrupts set before t1, even if masked. All interrupts, which are flagged after t1 remain active. After the ISTAU read access, the next unmasked interrupt will generate the next interrupt at time t2. After t2 it is possible to reprogram the MASKU register, so that all interrupts, which arrived between t1 and t2 are accessible. Data Sheet 100 2001-03-30 PEF 81912/81913 Functional Description * M56R 7 0 MS2 MS1 NEBE M61 M52 M51 0 FEBE + OPMODE.MLT CRC, TLL, no Filtering MFILT + M4R 7 AIB UOA M46 M45 M44 SCO DEA 0 ACT MFILT M4RMASK 7 UCIR CRC, TLL, no Filtering C/I C/I C/I 0 C/I EOCR 15 MFILT 11 a1 a2 TLL, CHG, no Filtering ISTAU 7 MLT CI FEBE/ NEBE M56 MASKU MLT CI FEBE/ NEBE M56 M4 EOC 6ms 12ms 7 0 i8 M4 EOC 6ms 0 12ms ISTA U Reserved MASK interr_U_Q2.vsd 0 INT Figure 49 Interrupt Structure U-Transceiver Data Sheet 101 2001-03-30 PEF 81912/81913 Functional Description 2.5 S-Transceiver The S-Transceiver offers the NT and LT-S mode state machines described in the User's Manual V3.4 [10]. The S-transceiver lies in IOM(R)-2 channel 1 (default) and is configured and controlled via the registers described in Chapter 4.7. The state machine is set to NT mode (default) but can be set to LT-S mode via register programming. The TE mode (S-transceiver TE mode, U-transceiver disabled) is not supported. 2.5.1 Line Coding, Frame Structure Line Coding The following figure illustrates the line code. A binary ONE is represented by no line signal. Binary ZEROs are coded with alternating positive and negative pulses with two exceptions: For the required frame structure a code violation is indicated by two consecutive pulses of the same polarity. These two pulses can be adjacent or separated by binary ONEs. In bus configurations a binary ZERO always overwrites a binary ONE. * 011 code violation Figure 50 S/T -Interface Line Code Frame Structure Each S/T frame consists of 48 bits at a nominal bit rate of 192 kbit/s. For user data (B1+B2+D) the frame structure applies to a data rate of 144 kbit/s (see Figure 50). In the direction TE NT the frame is transmitted with a two bit offset. For details on the framing rules please refer to ITU I.430 section 6.3. The following figure illustrates the standard frame structure for both directions (NT TE and TE NT) with all framing and maintenance bits. Data Sheet 102 2001-03-30 PEF 81912/81913 Functional Description * Figure 51 -F - L. -D -E - FA -N - B1 - B2 -A -S -M Frame Structure at Reference Points S and T (ITU I.430) Framing Bit D.C. Balancing Bit D-Channel Data Bit D-Channel Echo Bit Auxiliary Framing Bit B1-Channel Data Bit B2-Channel Data Bit Activation Bit S-Channel Data Bit Multiframing Bit F = (0b) identifies new frame (always positive pulse, always code violation) L. = (0b) number of binary ZEROs sent after the last L. bit was odd Signaling data specified by user E = D received E-bit is equal to transmitted D-bit See section 6.3 in ITU I.430 N = FA User data User data A = (0b) INFO 2 transmitted A = (1b) INFO 4 transmitted S1 channel data (see note below) M = (1b) Start of new multi-frame Note: The ITU I.430 standard specifies S1 - S5 for optional use. Data Sheet 103 2001-03-30 PEF 81912/81913 Functional Description 2.5.2 S/Q Channels, Multiframing According to ITU recommendation I.430 a multi-frame provides extra layer-1 capacity in the TE-to-NT direction through the use of an extra channel between the TE and NT (Qchannel). The Q bits are defined to be the bits in the FA bit position. In the NT-to-TE direction the S-channel bits are used for information transmission. The S- and Q-channels are accessed via C by reading/writing the SQR or SQX bits in the S/Q channel registers (SQRR, SQXR). Table 31 shows the S and Q bit positions within the multi-frame. Table 31 S/Q-Bit Position Identification and Multi-Frame Structure NT-to-TE NT-to-TE FA Bit Position M Bit ONE ZERO ZERO ZERO ZERO ONE ZERO ZERO ZERO ZERO ONE ZERO ZERO ZERO ZERO ONE ZERO ZERO ZERO ZERO ONE ZERO ONE ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ONE ZERO NT-to-TE S Bit S11 S21 S31 S41 S51 S12 S22 S32 S42 S52 S13 S23 S33 S43 S53 S14 S24 S34 S44 S54 S11 S21 TE-to-NT FA Bit Position Q1 ZERO ZERO ZERO ZERO Q2 ZERO ZERO ZERO ZERO Q3 ZERO ZERO ZERO ZERO Q4 ZERO ZERO ZERO ZERO Q1 ZERO Frame Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 Data Sheet 104 2001-03-30 PEF 81912/81913 Functional Description The S-transceiver starts multiframing if SQXR1.MFEN is set. After multi-frame synchronization has been established in the TE, the Q data will be inserted at the upstream (TE NT) FA bit position by the TE in each 5th S/T frame, the S data will be inserted at the downstream (NT TE) S bit position in each 5th S/T frame (see Table 31). Access to S2-S5-channel is not supported. Interrupt Handling for Multi-Framing To trigger the microcontroller for a multi-frame access an interrupt can be generated once per multi-frame (SQW) or if the received Q-channel have changed (SQC). In both cases the microcontroller has access to the multiframe within the duration of one multiframe (5 ms). The start of a multiframe can not be synchronized to an external signal. 2.5.3 Data Transfer between IOM(R)-2 and S0 In the state G3 (Activated) or if the internal layer-1 statemachine is disabled and XINF of register S_CMD is programmed to '011' the B1, B2 and D bits are transferred transparently from the S/T to the IOM(R)-2 interface and vice versa. In all other states '1's are transmitted to the IOM(R)-2 interface. Note: In intelligent NT or intelligent LT-S mode the D-channel access can be blocked by the IOM(R)-2 D-channel handler. 2.5.4 Loopback 2 C/I commands ARL and AIL close the analog loop as close to the S-interface as possible. ETSI refers to this loop under 'loopback 2'. ETSI requires, that B1, B2 and D channels have the same propagation delay when being looped back. The D-channel Echo bit is set to bin. 0 during an analog loopback (i.e. loopback 2). The loop is transparent. Note: After C/I-code AIL has been recognized by the S-transceiver, zeros are looped back in the B and D-channels (DU) for four frames. 2.5.5 Control of S-Transceiver / State Machine The S-transceiver activation/ deactivation can be controlled by an internal statemachine via the IOM(R)-2 C/I-channel or by software via the C interface directly. In the default state the internal layer-1 statemachine of the S-transceiver is used. By setting the L1SW bit in the S_CONF0 register the internal statemachine can be disabled and the layer-1 transmit commands, which are normally generated by the internal statemachine can be written directly into the S_CMD register or the received status read out from the S_STA register, respectively. The S-transceiver layer-1 control flow is shown in Figure 52. Data Sheet 105 2001-03-30 PEF 81912/81913 Functional Description * Disable internal Statemachine (S_CONF.L1SW) C/I Command IOM-2 C/I Indication Layer-1 State Machine Transmit Command Register INFO for Transmitter Transmitter (S_CMD) Receive Status Register INFO Receiver of Receiver (S_STA) Layer-1 Control C-Interface macro_14 Figure 52 S-Transceiver Control The state diagram notation is given in Figure 53. The information contained in the state diagrams are: - - - - - - state name Signal received from the line interface (INFO) Signal transmitted to the line interface (INFO) C/I code received (commands) C/I code transmitted (indications) transition criteria The transition criteria are grouped into: - C/I commands - Signals received from the line interface (INFOs) - Reset Data Sheet 106 2001-03-30 PEF 81912/81913 Functional Description * OUT IN IOM-2 Interface C/I code Ind. Cmd. S ta te Unconditional Transition S/T Interface INFO ix ir macro_17.vsd Figure 53 State Diagram Notation As can be seen from the transition criteria, combinations of multiple conditions are possible as well. A "" stands for a logical AND combination. And a "+" indicates a logical OR combination. Test Signals * 2 kHz Single Pulses (TM1) One pulse with a width of one bit period per frame with alternating polarity. * 96 kHz Continuous Pulses (TM2) Continuous pulses with a pulse width of one bit period. Note: The test signals TM1 and TM2 are invoked via C/I codes `TM1` and `TM2` according to Chapter 2.5.5.1. External Layer-1 Statemachine Instead of using the integrated layer-1 statemachine it is also possible to implement the layer-1 statemachine completely in software. The internal layer-1 statemachine can be disabled by setting the L1SW bit in the S_CONF0 register to '1'. The transmitter is completely under control of the microcontroller via register S_CMD. The status of the receiver is stored in register S_STA and has to be evaluated by the microcontroller. This register is updated continuously. If not masked a RIC interrupt is generated by any change of the register contents. The interrupt is cleared after a read access to this register. Reset States After an active signal on the reset pin RST the S-transceiver state machine is in the reset state. Data Sheet 107 2001-03-30 PEF 81912/81913 Functional Description C/I Codes in Reset State In the reset state the C/I code 0000 (TIM) is issued. This state is entered either after a hardware reset (RST) or with the C/I code RES. C/I Codes in Deactivated State If the S-transceiver is in state `Deactivated` and receives i0, the C/I code 0000 (TIM) is issued until expiration of the 8 ms timer. Otherwise, the C/I code 1111 (DI) is issued. 2.5.5.1 C/I Codes The table below presents all defined C/I0 codes. A command needs to be applied continuously until the desired action has been initiated. Indications are strictly state orientated. Refer to the state diagrams in the following sections for commands and indications applicable in various states. * LT-S Code 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Cmd DR RES TM1 TM2 - - - - AR - ARL - - - - DC Ind TIM - - - RSY - - - AR - - CVR AI - - DI NT Cmd DR RES TM1 TM2 RSY - - - AR - ARL - AI - AIL DC Ind TIM - - - RSY - - - AR - - CVR AI - - DI Data Sheet 108 2001-03-30 PEF 81912/81913 Functional Description Receive Infos on S/T I0 I0 I3 I3 INFO 0 detected Level detected (signal different to I0) INFO 3 detected Any INFO other than INFO 3 Transmit Infos on S/T I0 I2 I4 It INFO 0 INFO 2 INFO 4 Send Single Pulses (TM1). Send Continuous Pulses (TM2). Data Sheet 109 2001-03-30 PEF 81912/81913 Functional Description 2.5.5.2 * State Machine NT Mode RST TIM RES Reset i0 RES Any State * DC DI ARD1) DR ARD1) TIM DR DR TM1 TIM TM2 Test Mode i it DC * TM1 TM2 Any State G4 Pend. Deact. i0 i0 (i0*16ms)+32ms DR G4 Wait for DR i0 * DC DI TIM DR DC G1 Deactivated ARD1) i0 i0 (i0*8ms) AR DC DR G1 i0 Detected i0 * ARD1) AR ARD G2 Pend. Act i2 i3 i3 AID RSY ARD G2 Lost Framing S/T i2 RSY DR RSY RSY G3 Lost Framing U i2 * RSY i3 ARD1) AID2) i3*ARD AI i3*ARD1) i3*AID2) RSY AID2) i3*AID2) AI AID DR ARD1) ARD DR DR G2 Wait for AID i2 i3 G3 Activated i4 i3 1) 2): : ARD = AR or ARL AID =AI or AIL statem_nt_s.vsd Figure 54 State Machine NT Mode Note: State 'Test Mode' can be entered from any state except from state 'Test Mode' itself, i.e. C/I-code 'TMi' must not be followed by C/I-code 'TMj' directly. Data Sheet 110 2001-03-30 PEF 81912/81913 Functional Description G1 Deactivated The S-transceiver is not transmitting. There is no signal detected on the S/T-interface, and no activation command is received in the C/I channel. Activation is possible from the S/T interface and from the IOM(R)-2 interface. G1 I0 Detected An INFO 0 is detected on the S/T-interface, translated to an "Activation Request" indication in the C/I channel. The S-transceiver is waiting for an AR command, which normally indicates that the transmission line upstream is synchronized. G2 Pending Activation As a result of the ARD command, an INFO 2 is sent on the S/T-interface. INFO 3 is not yet received. In case of ARL command, loop 2 is closed. G2 wait for AID INFO 3 was received, INFO 2 continues to be transmitted while the S-transceiver waits for a "switch-through" command AID from the device upstream. G3 Activated INFO 4 is sent on the S/T-interface as a result of the "switch through" command AID: the B and D-channels are transparent. On the command AIL, loop 2 is closed. G2 Lost Framing S/T This state is reached when the transceiver has lost synchronism in the state G3 activated. G3 Lost Framing U On receiving an RSY command which usually indicates that synchronization has been lost on the transmission line, the S-transceiver transmits INFO 2. G4 Pending Deactivation This state is triggered by a deactivation request DR, and is an unstable state. Indication DI (state "G4 wait for DR") is issued by the transceiver when: either INFO0 is received for a duration of 16 ms or an internal timer of 32 ms expires. Data Sheet 111 2001-03-30 PEF 81912/81913 Functional Description G4 wait for DR Final state after a deactivation request. The S-transceiver remains in this state until DC is issued. Unconditional States Test Mode TM1 Send Single Pulses Test Mode TM2 Send Continuous Pulses C/I Commands * Command Deactivation Request Reset Abbr. DR RES Code 0000 0001 Remark Deactivation Request. Initiates a complete deactivation by transmitting INFO 0. Reset of state machine. Transmission of Info0. No reaction to incoming infos. RES is an unconditional command. Send Single Pulses. Send Continuous Pulses. Receiver is not synchronous Activation Request. This command is used to start an activation. Activation request loop. The transceiver is requested to operate an analog loop-back close to the S/T-interface. Activation Indication. Synchronous receiver, i.e. activation completed. Send Single Pulses Send Continuous Pulses Receiver not Synchronous Activation Request Activation Request Loop Activation Indication TM1 TM2 RSY AR ARL 0010 0011 0100 1000 1010 AI 1100 Data Sheet 112 2001-03-30 PEF 81912/81913 Functional Description Command Activation Indication Loop Deactivation Confirmation Abbr. AIL DC Code 1110 1111 Remark Activation Indication Loop Deactivation Confirmation. Transfers the transceiver into a deactivated state in which it can be activated from a terminal (detection of INFO 0 enabled). Remark Interim indication during deactivation procedure. Receiver is not synchronous. INFO 0 received from terminal. Activation proceeds. Illegal code violation received. This function has to be enabled in S_CONF0.EN_ICV. Synchronous receiver, i.e. activation completed. Timer (32 ms) expired or INFO 0 received for a duration of 16 ms after deactivation request. Indication Timing Receiver not Synchronous Activation Request Illegal Code Ciolation Activation Indication Deactivation Indication Abbr. TIM RSY AR CVR AI DI Code 0000 0100 1000 1011 1100 1111 Data Sheet 113 2001-03-30 PEF 81912/81913 Functional Description 2.5.5.3 * State Machine LT-S Mode RST TIM RES Reset i0 RES Any State * DC DI ARD 1) TIM DR ARD 1) DR DR TM1 TIM TM2 Test Mode i it DC * TM1 TM2 Any State G4 Pend. Deact. i0 i0 (i0*16ms)+32ms DR G4 Wait for DR i0 * DC DI TIM DC DR G1 Deactivated i0 i0 (i0*8ms)+ARD1) DC AR ARD G2 Pend. Act. i2 i3 i3 DC RSY ARD G2 Lost Framing S/T i2 i3 DR i3 AI i3 DC ARD DR DR G3 Activated i4 i3 1) : ARD = AR or ARL statem_lts_s.vsd Figure 55 State Machine LT-S Mode Note: State 'Test Mode' can be entered from any state except from state 'Test Mode' itself, i.e. C/I-code 'TMi' must not be followed by C/I-code 'TMj 'directly. Data Sheet 114 2001-03-30 PEF 81912/81913 Functional Description G1 deactivated The S-transceiver is not transmitting. There is no signal detected on the S/T-interface, and no activation command is received in the C/I channel. Activation is possible from the S/T interface and from the IOM(R)-2 interface. G2 pending activation As a result of an INFO 0 detected on the S/T line or an ARD command, the S-transceiver begins transmitting INFO 2 and waits for reception of INFO 3. The timer to supervise reception of INFO 3 is to be implemented in software. In case of an ARL command, loop 2 is closed. G3 activated Normal state where INFO 4 is transmitted to the S/T-interface. The transceiver remains in this state as long as neither a deactivation nor a test mode is requested, nor the receiver looses synchronism. When receiver synchronism is lost, INFO 2 is sent automatically. After reception of INFO 3, the transmitter keeps on sending INFO 4. G2 lost framing This state is reached when the S-transceiver has lost synchronism in the state G3 activated. G4 pending deactivation This state is triggered by a deactivation request DR. It is an unstable state: indication DI (state "G4 wait for DR.") is issued by the S-transceiver when: either INFO0 is received for a duration of 16 ms, or an internal timer of 32 ms expires. G4 wait for DR Final state after a deactivation request. The transceiver remains in this state until DC is issued. Unconditional States Test mode - TM1 Single alternating pulses are sent on the S/T-interface. Data Sheet 115 2001-03-30 PEF 81912/81913 Functional Description Test mode - TM2 Continuous alternating pulses are sent on the S/T-interface. * Command Deactivation Request Abbr. DR Code 0000 Remark DR - Deactivation Request. Initiates a complete deactivation by transmitting INFO 0. Reset of state machine. Transmission of Info0. No reaction to incoming infos. RES is an unconditional command. Send Single Pulses. Send Continuous Pulses. Activation Request. This command is used to start an activation. Activation request loop. The transceiver is requested to operate an analog loop-back close to the S/T-interface. Deactivation Confirmation. Transfers the transceiver into a deactivated state in which it can be activated from a terminal (detection of INFO 0 enabled). Remark Interim indication during activation procedure in G1. Receiver is not synchronous INFO 0 received from terminal. Activation proceeds. Illegal code violation received. This function has to be enabled in S_CONF0.EN_ICV. Synchronous receiver, i.e. activation completed. Timer (32 ms) expired or INFO 0 received for a duration of 16 ms after deactivation request Reset RES 0001 Send Single Pulses Send Continuous Pulses Activation Request Activation Request Loop Deactivation Confirmation TM1 TM2 AR ARL 0010 0011 1000 1010 DC 1111 Indication Timing Receiver not Synchronous Activation Request Illegal Code Ciolation Activation Indication Deactivation Indication Abbr. TIM RSY AR CVR AI DI Code 0000 0100 1000 1011 1100 1111 Data Sheet 116 2001-03-30 PEF 81912/81913 Functional Description 2.5.6 S-Transceiver Enable / Disable The layer-1 part of the S-transceiver can be enabled/disabled with the two bits S_CONF0.DIS_TR and S_CONF2.DIS_TX. If DIS_TX='1' the transmit buffers are disabled. The receiver will monitor for incoming data in this configuration. By default the transmitter is disabled (DIS_TX = '1'). If the transceiver is disabled (DIS_TR = '1', DIS_TX = don't care) all layer-1 functions are disabled including the level detection circuit of the receiver. In this case the power consumption of the S-transceiver is reduced to a minimum. Data Sheet 117 2001-03-30 PEF 81912/81913 Functional Description 2.5.7 * Interrupt Structure S-Transceiver Level Detect S_STA 7 RINF 0 FECV 0 FSYN 0 0 LD SQRR 7 MSYN MFEN 0 0 SQR1 SQR2 SQR3 0 SQR4 SQXR 7 0 MFEN 0 0 SQX1 SQX2 SQX3 0 SQX4 7 ISTAS 0 0 0 0 LD RIC SQC 0 SQW MASKS 1 1 1 1 LD RIC SQC SQW S 7 Reserved ISTA MASK 0 INT interr.vsd Figure 56 Interrupt Structure S-Transceiver Data Sheet 118 2001-03-30 PEF 81912/81913 Functional Description 2.6 HDLC Controller The Q-SMINT(R)IX contains a HDLC controller which can be used for the layer-2 functions of the D- channel protocol (LAPD) or B-channel protocols. By setting the enable HDLC channel bits (EN_D, EN_B1H, EN_B2H) in the HCI_CR register the HDLC controller can access the D or B-channels or any combination of them e.g. 18 bit IDSL data (2B+D). The HDLC transceiver in the Q-SMINT(R)IX performs the framing functions used in HDLC based communication: flag generation/recognition, bit stuffing, CRC check and address recognition. The HDLC controller contains a 64 byte FIFO in both receive and transmit direction which is implemented as a cyclic buffer. The transceivers read and write data sequentially with constant data rate, whereas the data transfer between FIFO and C interface uses a block oriented protocol with variable block sizes. 2.6.1 Message Transfer Modes The HDLC controller can be programmed to operate in various modes, which are different in the treatment of the HDLC frame in receive direction. Thus, the receive data flow and the address recognition features can be programmed in a flexible way to satisfy different system requirements. The structure of a LAPD two-byte address is shown below. * High Address Byte SAPI1, 2, SAPG C/R 0 Low Address Byte TEI 1, 2, TEIG EA For the address recognition the Q-SMINT(R)IX contains four programmable registers for individual SAPI and TEI values (SAP1, 2 and TEI1, 2), plus two fixed values for the "group" SAPI (SAPG = 'FE' or 'FC') and TEI (TEIG = 'FF'). The received C/R bit is excluded from the address comparison. EA is the address field extension bit which is set to '1' according to the LAPD protocol. There are 5 different operating modes which can be selected via the mode selection bits MDS2-0 in the MODEH register: Non-Auto Mode (MDS2-0 = '01x') Characteristics: Full address recognition with one-byte (MDS = '010') or two-byte (MDS = '011') address comparison All frames with valid addresses are accepted and the bytes following the address are transferred to the P via RFIFO. Additional information is available in RSTA. Data Sheet 119 2001-03-30 PEF 81912/81913 Functional Description Transparent mode 0 (MDS2-0 = '110'). Characteristics: no address recognition Every received frame is stored in RFIFO (first byte after opening flag to CRC field). Additional information can be read from RSTA. Transparent mode 1 (MDS2-0 = '111'). Characteristics: SAPI recognition A comparison is performed on the first byte after the opening flag with SAP1, SAP2 and "group" SAPI (FEH/FCH). In the case of a match, all the following bytes are stored in RFIFO. Additional information can be read from RSTA. Transparent mode 2 (MDS2-0 = '101'). Characteristics: TEI recognition A comparison is performed only on the second byte after the opening flag, with TEI1, TEI2 and group TEI (FFH). In case of a match the rest of the frame is stored in the RFIFO. Additional information is available in RSTA. Extended transparent mode (MDS2-0 = '100'). Characteristics: fully transparent In extended transparent mode fully transparent data transmission/reception without HDLC framing is performed i.e. without FLAG generation/recognition, CRC generation/ check and bitstuffing mechanism. This allows user specific protocol variations. Also refer to Chapter 2.6.5. 2.6.2 2.6.2.1 Data Reception Structure and Control of the Receive FIFO The 64-byte cyclic RFIFO buffer has variable FIFO block sizes (thresholds) of 4, 8, 16 or 32 bytes which can be selected by setting the corresponding RFBS bits in the EXMR register. The variable block size allows an optimized HDLC processing concerning frame length, I/O throughput and interrupt load. The transfer protocol between HDLC FIFO and microcontroller is block orientated with the microcontroller as master. The control of the data transfer between the CPU and the Q-SMINT(R)IX is handled via interrupts (Q-SMINT(R)IX Host) and commands (Host Q-SMINT(R)IX). There are three different interrupt indications in the ISTAH register concerned with the reception of data: - RPF (Receive Pool Full) interrupt, indicating that a data block of the selected length (EXMR.RFBS) can be read from RFIFO. The message which is currently received exceeds the block size so further blocks will be received to complete the message. Data Sheet 120 2001-03-30 PEF 81912/81913 Functional Description - RME (Receive Message End) interrupt, indicating that the reception of one message has been completed and the message has been stored in the RFIFO. Either - a short message has been received (message length the defined block size (EXMR.RFBS) or - the last part of a long message has been received (message length > the defined block size (EXMR.RFBS)). - RFO (Receive Frame Overflow) interrupt, indicating that a complete frame could not be stored in RFIFO and is therefore lost as the RFIFO is occupied. This occurs if the host fails to respond quick enough to RPF/RME interrupts since previous data was not read by the host. There are two control commands that are used with the reception of data: - RMC (Receive Message Complete) command, telling the Q-SMINT(R)IX that a data block has been read from the RFIFO and the corresponding FIFO space can be released for new receive data. - RRES (Receiver Reset) command, resetting the HDLC receiver and clearing the receive FIFO of any data (e.g. used before start of reception). It has to be used after a change of the message transfer mode. RRES does not clear pending interrupt indications of the receiver, but have to be be cleared by reading these interrupts. Note: The significant interrupts and commands are underlined as only these are usually used during a normal reception sequence. The following description of the receive FIFIO operation is illustrated in Figure 57 for a RFIFO block size (threshold) of 16 and 32 bytes. The RFIFO requests service from the microcontroller by setting a bit in the ISTAH register, which causes an interrupt (RPF, RME, RFO). The microcontroller then reads status information (RBCH,RBCL), data from the RFIFO and changes the RFIFO block size (EXMR.RFBS). A block transfer is completed by the microcontroller via a receive message complete (CMDR.RMC) command. This causes the space of the transferred bytes being released for new data and in case the frame was complete (RME) the reset of the receive byte counter RBC (RBCH,RBCL).1) The total length of the frame is contained in the RBCH and RBCL registers which contain a 12 bit number (RBC11...0), so frames up to 4095 byte length can be counted. If a frame is longer than 4095 bytes, the RBCH.OV (overflow) bit will be set. The least significant bits of RBCL contain the number of valid bytes in the last data block indicated by RME (length of last data block selected block size). Table 32 shows which RBC bits contain the number of bytes in the last data block or number of complete data blocks, 1) If RMC is omitted, then no new interrupt can be generated. Data Sheet 121 2001-03-30 PEF 81912/81913 Functional Description respectively. If the number of bytes in the last data block is '0' the length of the last received block is equal to the block size. * Table 32 EXMR.RFBS bits '00' '01' '10' '11' Receive Byte Count with RBC11...0 in the RBCH and RBCL registers Selected block size 32 byte 16 byte 8 byte 4 byte Number of complete data blocks in RBC11...5 RBC11...4 RBC11...3 RBC11...2 bytes in the last data block in RBC4...0 RBC3...0 RBC2...0 RBC1...0 The transfer block size (EXMR.RFBS) is 32 bytes by default. If it is necessary to react to an incoming frame within the first few bytes the microcontroller can set the RFIFO block size to a smaller value. Each time a CMDR.RMC or CMDR.RRES command is issued, the RFIFO access controller sets its block size to the value specified in EXMR.RFBS, so the microcontroller has to write the new value for RFBS before the RMC command. When setting an initial value for RFBS before the first HDLC activities, a RRES command must be issued afterwards. The RFIFO can hold any number of frames fitting in the 64 bytes independent on RFBS. At the end of a frame, the RSTA byte is always inserted. All generated interrupts are inserted together with all additional information into a wait line to be individually passed to the host. For example if several data blocks have been received to be read by the host and the host acknowledges the current block, a new RPF or RME interrupt from the wait line is immediately generated to indicate new data. Data Sheet 122 2001-03-30 PEF 81912/81913 Functional Description * RAM EXMR.RFBS=11 so after the first 4 bytes of a new frame have been stored in the fifo a receive pool full interrupt ISTAH.RPF is set. The P has read the 4 bytes, sets RFBS=01 (16 bytes) and completes the block transfer by a CMDR.RMC command. Following CMDR.RMC the 4 bytes of the last block are deleted. RAM 32 RFACC 32 RFACC RFIFO ACCESS CONTROLLER 16 RFBS=11 8 RFIFO ACCESS CONTROLLER 16 RFBS=01 8 4 HDLC Receiver RFIFO 4 HDLC Receiver RPF EXMR.RFBS=01 RMC P RAM HDLC Receiver RSTA RBC=4h RAM 32 RFACC HDLC Receiver RSTA 32 RFACC The HDLC receiver has written further data into the FIFO. When a frame is complete, a status byte (RSTA) is appended. Meanwhile two more short frames have been received. RFIFO ACCESS RSTA RSTA RFIFO ACCESS 16 CONTROLLER RFBS=01 8 RSTA RSTA 16 CONTROLLER RFBS=01 8 RBC=14h RBC=16h P RFIFO RFIFO FIFO. RMC P When the RFACC detects 16 valid bytes, it sets a RPF interrupt. The P reads the 16 bytes and acknowledges the transfer by setting CMDR.RMC. This causes the space occupied by the 16 bytes being released. After the RMC acknowledgement the RFACC detects a RSTA byte, i.e. end of the frame, therefore it asserts a RME interupt and increments the RBC counter by 2. Figure 57 RFIFO Operation Data Sheet 123 RME RPF 2001-03-30 PEF 81912/81913 Functional Description Possible Error Conditions during Reception of Frames If parts of a frame get lost because the receive FIFO is full, the Receive Data Overflow (RDO) byte in the RSTA byte will be set. If a complete frame is lost, i.e. if the FIFO is full when a new frame is received, the receiver will assert a Receive Frame Overflow (RFO) interrupt. The microcontroller sees a cyclic buffer, i.e. if it tries to read more data than available, it reads the same data again and again. On the other hand, if it does not read or does not want to read all data, they are deleted anyway after the RMC command. If the microcontroller tries to read data without a prior RME or RPF interrupt, the content of the RFIFO would not be corrupted, but new data is only transferred to the host as long as new valid data is available in the RFIFO, otherwise the last data is read again and again. The general procedures for a data reception sequence are outlined in the flow diagram in Figure 58. Data Sheet 124 2001-03-30 PEF 81912/81913 Functional Description * START Receive Message End RME ? N Receive Pool Full RPF ? Y Read Counter RD_Count := RFBS or RD_Count := RBC Y N Read RBC RD_Count := RBC Read RD_Count bytes from RFIFO 1) * Change Block Size Write EXMR.RFBS (optional) Receive Message Complete Write RMC RBC = RBCH + RBCL register RFBS: Refer to EXMR register 1) * In case of RME the last byte in RFIFO contains the receive status information RSTA HDLC_Rflow.vsd Figure 58 Data Reception Procedures Figure 59 gives an example of an interrupt controlled reception sequence, supposed that a long frame (68 byte) followed by two short frames (12 byte each) are received. The FIFO threshold (block size) is set to 32 bytes (EXMR.RFBS = '00') in this example: * After 32 bytes have been received off frame 1 a RPF interrupt is generated to indicate that a data block can be read from the RFIFO. Data Sheet 125 2001-03-30 PEF 81912/81913 Functional Description * The host reads the first data block from RFIFO and acknowledges the reception by RMC. Meanwhile the second data block is received and stored in RFIFO. * The second 32 byte block is indicated by RPF which is read and acknowledged by the host as described before. * The reception of the remaining 4 bytes are indicated by RME (i.e. the receive status in RSTA register is always appended to the end of a frame). * The host gets the number of received bytes (COUNT = 5) from RBCL/RBCH and reads out the RFIFO and optionally the status register RSTA. The frame is acknowledged by RMC. * The second frame is received and indicated by RME interrupt. * The host gets the number of bytes (COUNT = 13) from RBCL/RBCH and reads out the RFIFO and status registers. The RFIFO is acknowledged by RMC. * The third frame is transferred in the same way. * IOM Interface Receive Frame 32 68 Bytes 32 4 12 12 Bytes Bytes 12 12 RD 32 Bytes RPF RD 32 Bytes RD RD Count 5 Bytes 1) * RD RD Count 13 Bytes 1) * RD RD Count 13 Bytes 1) * RMC RPF RMC RME RMC RME RMC RME RMC CPU Interface 1) * The last byte contains the receive status information fifoseq_rec.vsd Figure 59 Reception Sequence Example 2.6.2.2 Receive Frame Structure The management of the received HDLC frames as affected by the different operating modes (see Chapter 2.6.1) is shown in Figure 60. Data Sheet 126 2001-03-30 PEF 81912/81913 Functional Description * FLAG MDS 0 S S S * ADDR DDSS D CTRL I CRC SS FLAG MDS MDS0 MD * S * * 0 0 * S * * * 0 0 * S * S S S * * S * 0 * S * * DS * * M MS S S macro_12.vsd S * * Figure 60 Receive Data Flow Note: The figure shows all modes except the extended transparent mode as this mode uses no typical frame structure or address recognition. Data is transferred purely transparent. Data Sheet 127 2001-03-30 PEF 81912/81913 Functional Description The Q-SMINT(R)IX indicates to the host that a new data block can be read from the RFIFO by means of a RPF interrupt (see previous chapter). User data is stored in the RFIFO and information about the received frame is available in the RSTA, RBCL and RBCH registers which are listed in Table 33. Table 33 Information Type of frame (Command/ Response) Recognition of SAPI Receive Information at RME Interrupt Register RSTA Bit C/R Mode Non-auto mode, 2-byte address field Transparent mode 1 Non-auto mode, 2-byte address field Transparent mode 1 All except transparent mode 0 and 1 All All All All All (see Table 32) All All RSTA SA1, 0 Recognition of TEI Result of CRC check (correct/incorrect) Valid Frame Abort condition detected (yes/no) RSTA RSTA RSTA RSTA TA CRC VFR RAB RDO RBCx-0 RBC11-0 OV Data overflow during reception of RSTA a frame (yes/no) Number of bytes received in RFIFO Message length RFIFO Overflow RBCL RBCL RBCH RBCH The RSTA register is appended as last byte to the end of a frame. 2.6.3 2.6.3.1 Data Transmission Structure and Control of the Transmit FIFO The 64-byte cyclic XFIFO buffer has variable FIFO block sizes (thresholds) of 16 or 32 bytes, selectable by the XFBS bit in the EXMR register. There are three different interrupt indications in the ISTAH register concerned with the transmission of data: Data Sheet 128 2001-03-30 PEF 81912/81913 Functional Description - XPR (Transmit Pool Ready) interrupt, indicating that a data block of up to 16 or 32 bytes (block size selected via EXMR:XFBS) can be written to the XFIFO. A XPR interrupt is generated either - after a XRES (Transmitter Reset) command (which is issued for example for frame abort) or - when a data block from the XFIFO is transmitted and the corresponding FIFO space is released to accept further data from the host. - XDU (Transmit Data Underrun) interrupt, indicating that the transmission of the current frame has been aborted (seven consecutive '1's are transmitted) as the XFIFO holds no further transmit data. This occurs if the host fails to respond to a XPR interrupt quick enough. - XMR (Transmit Message Repeat) interrupt, indicating that the transmission of the complete last frame has to be repeated as a collision on the S bus has been detected while the first data bytes have already been overwritten with new data. So the XFIFO does not hold the first data bytes of the frame (the HDLC transmitter is stopped if a collision on the S bus has been detected). The occurrence of a XDU or XMR interrupt clears the XFIFO and a XPR interrupt is issued together with a XDU or XMR interrupt, respectively. Data cannot be written to the XFIFO as long as a XDU/XMR interrupt is pending. Three different control commands are used for transmission of data: - XTF (Transmit Transparent Frame) command, telling the Q-SMINT(R)IX that up to 16 or 32 bytes (according to selected block size) have been written to the XFIFO and should be transmitted. A start flag is generated automatically. - XME (Transmit Message End) command, telling the Q-SMINT(R)IX that the last data block written to the XFIFO completes the corresponding frame and should be transmitted. This implies that according to the selected mode a frame end (CRC + closing flag) is generated and appended to the frame. - XRES (Transmitter Reset) command, resetting the HDLC transmitter and clearing the transmit FIFO of any data. After a XRES command the transmitter always sends an abort sequence, i.e. this command can be used to abort a transmission. XRES does not clear pending interrupt indications of the transmitter, but has to be be cleared by reading these interrupts. Optionally two additional status conditions can be read by the host: - XDOV (Transmit Data Overflow), indicating that the data block size has been exceeded, i.e. more than 16 or 32 bytes were entered and data was overwritten. - XFW (Transmit FIFO Write Enable), indicating that data can be written to the XFIFO. This status flag may be polled instead of or in addition to XPR. Note: The significant interrupts and commands are underlined as only these are usually used during a normal transmission sequence. Data Sheet 129 2001-03-30 PEF 81912/81913 Functional Description The XFIFO requests service from the microcontroller by setting a bit in the ISTAH register, which causes an interrupt (XPR, XDU, XMR). The microcontroller can then read the status register STAR (XFW, XDOV), write data in the FIFO and it may optionally change the transmit FIFO block size (EXMR.XFBS) if required. The instant of the initiation of a transmit pool ready (XPR) interrupt after different transmit control commands is listed in Table 34. * Table 34 CMDR. XTF XTF & XME XME XPR Interrupt (availability of the XFIFO) after XTF, XME Commands Transmit pool ready (XPR) interrupt initiated... as soon as the selected buffer size in the FIFO is available after the successful transmission of the closing flag. The transmitter always sends an abort sequence as soon as the selected buffer size in the FIFO is available, two consecutive frames share flags (endflag = startflag of next frame). When setting XME the transmitter appends the FCS and the endflag at the end of the frame. When XTF & XME have been set, the XFIFO is locked until successful transmission of the current frame, so a consecutive XPR interrupt also indicates successful transmission of the frame, whereas after XME the XPR interrupt is asserted as soon as there is space for one data block in the XFIFO. The transfer block size is 32 bytes by default, but sometimes, if the microcontroller has a high computational load, it is useful to increase the maximum reaction time for a XPR interrupt. The maximum reaction time is: tmax = (XFIFO size - XFBS) / data transmission rate With a selected block size of 16 bytes indicates a XPR interrupt when there are still 48 bytes (64 bytes - 16 bytes) to be transmitted. With a 32 bytes block size the XPR is initiated when there are still 32 bytes (64 bytes - 32 bytes), i.d. the maximum reaction time for the smaller block size is 50 % higher with the trade-off of a doubled interrupt load. A selected block size of 32 or 16 bytes respectively always indicates the available space in the XFIFO. So any number of bytes smaller than the selected XFBS may be stored in the FIFO during one "write block" access cycle. Similar to RFBS for the receive FIFO, a new setting of XFBS takes effect after the next XTF,XME or XRES command. XRES resets the XFIFO. The XFIFO can hold any number of frames fitting in the 64 bytes. Data Sheet 130 2001-03-30 PEF 81912/81913 Functional Description Possible Error Conditions during Transmission of Frames If the transmitter sees an empty FIFO, i.e. if the microcontroller does not react quickly enough to a XPR interrupt, a XDU (transmit data underrun) interrupt will be raised. If the HDLC channel becomes unavailable during transmission the transmitter tries to repeat the current frame as specified in the LAPD protocol. This is impossible after the first data block has been sent (16 or 32 bytes), in this case a XMR transmit message repeat interrupt is set and the microcontroller has to send the whole frame again. If the host fails to respond to a Transmit Pool Ready (XPR) interrupt quickly enough, then transmission of the current frame is aborted, a Transmit Data Underrun (XDU) interrupt is generated and an Abort Sequence (seven consecutive '1') shall be transmitted. If the C requests transmission of a new frame during a certain time window after the XDU interrupt, then the Abort Sequence may be overwritten by the Start Flag of this new frame. However, the Abort Sequence is transmitted correctly by waiting 8 IOM-2 frames before the C requests transmission of a new frame: * Read from address 20H (register ISTAH): 14H (XPR and XDU interrupt active) * Wait for 1 ms (e.g. by use of the internal timer of the Q-SMINTIX) * Write new frame to XFIFO Both XMR and XDU interrupts cause a reset of the XFIFO. The XFIFO is locked while a XMR or XDU interrupt is pending, i.e. all write actions of the microcontroller will be ignored as long as the microcontroller has not read the ISTAH register with the set XDU, XMR interrupts. If the microcontroller writes more data than allowed (16 or 32 bytes) , then the data in the XFIFO will be corrupted and the STAR.XDOV bit is set. If this happens, the microcontroller has to abort the transmission by CMDR.XRES and start new. The general procedures for a data transmission sequence are outlined in the flow diagram in Figure 61. Data Sheet 131 2001-03-30 PEF 81912/81913 Functional Description * START N Transmit Pool Ready XPR ? Y Command XTF Write Data (up to 32 Bytes) to XFIFO N End of Message ? Y Issue Command - XME or - XTF+XME End macro_13.vsd Figure 61 Data Transmission Procedure The following description gives an example for the transmission of a 76 byte frame with a selected block size of 32 byte (EXMR:XFBS=0): * The host writes 32 bytes to the XFIFO, issues a XTF command and waits for a XPR interrupt in order to continue with entering data. * The Q-SMINT(R)IX immediately issues a XPR interrupt (as remaining XFIFO space is not used) and starts transmission. * Due to the XPR interrupt the host writes the next 32 bytes to the XFIFO, followed by the XTF command, and waits for XPR. Data Sheet 132 2001-03-30 PEF 81912/81913 Functional Description * As soon as the last byte of the first block is transmitted, the Q-SMINT(R)IX issues a XPR interrupt (XFIFO space of first data block is free again) and continues transmitting the second block. * The host writes the remaining 12 bytes of the frame to the XFIFO and issues the XTF command together with XME to indicate that this is the end of frame. * After the last byte of the frame has been transmitted the Q-SMINT(R)IX releases a XPR interrupt and the host may proceed with transmission of a new frame. IOM Interface Transmit Frame 32 76 Bytes 32 12 WR 32 Bytes WR 32 Bytes XTF XPR XTF WR 12 Bytes XPR XTF+XME XPR CPU Interface fifoseq_tran.vsd Figure 62 Transmission Sequence Example 2.6.3.2 Transmit Frame Structure The transmission of transparent frames (XTF command) is shown in Figure 63. For transparent frames, the whole frame including address and control field must be written to the XFIFO. The host configures whether the CRC is generated and appended to the frame (default) or not (selected in EXMR.XCRC). Further, the host selects the interframe time fill signal which is transmitted between HDLC frames (EXMR:ITF). One option is to send continuous flags ('01111110'), or an idle sequence (continuous '1's are transmitted), which is used if D-channel access handling (collision resolution on the S bus) is required for example. Reprogramming of ITF takes effect only after the transmission of the current frame has been completed or after a XRES command. Data Sheet 133 2001-03-30 PEF 81912/81913 Functional Description FLAG ADDR T T FF CTRL I CRC FLAG Transmit Transparent Frame TF * * Te is enerate eat is set n is appene fifoflow_tran.vsd Figure 63 Transmit Data Flow 2.6.4 Access to IOM(R)-2 channels By setting the enable HDLC data bits (EN_D, EN_B1H, EN_B2H) in the HCI_CR register the HDLC controller can access the D, B1, B2 channels or any combination of them (e.g. 18 bit IDSL data (2B+D). In all modes (except extended transparent mode) sending works always frame aligned, i.e. it starts with the first selected channel whereas reception looks for a flag anywhere in the serial data stream. 2.6.5 Extended Transparent Mode This non-HDLC mode is selected by setting MODEH.MDS2-0 to '100'. In extended transparent mode fully transparent data transmission/reception without HDLC framing is performed i.e. without FLAG generation/recognition, CRC generation/check, bitstuffing mechanism. This allows user specific protocol variations. Transmitter The transmitter sends the data out of the FIFO without manipulation. Transmission is always IOM(R)-2-frame aligned and byte aligned, i.e. transmission starts in the first selected channel (B1, B2, D, according to the setting of register HCI_CR in the IOM(R)-2 Handler) of the next IOM(R)-2 frame. The FIFO indications and commands are the same as in other modes. If the microcontroller sets XTF & XME the transmitter responds with a XPR interrupt after sending the last byte, then it returns to its idle state (sending continuous `1'). Data Sheet 134 2001-03-30 PEF 81912/81913 Functional Description If the collision detection is enabled (MODEH.DIM = '0x1') the stop go bit (S/G) can be used as a clear-to-send indication as in any other mode. If the S/G bit is set to '1' (stop) during transmission the transmitter responds always with a XMR (transmit message repeat) interrupt and stops transmission. If the microcontroller fails to respond to a XPR interrupt in time and the transmitter runs out of data then it will assert a XDU (transmit data underrun) interrupt. Receiver The reception is IOM(R)-2-frame aligned and byte aligned, like transmission, i.e. reception starts in the first selected channel (B1, B2, D, according to the setting of register HCI_CR in the IOM(R)-2 Handler) of the next IOM(R)-2 frame. The FIFO indications and commands are the same as in others modes. All incoming data bytes are stored in the RFIFO. If the FIFO is full a RFO interrupt is asserted (EXMR.SRA = '0'). Note: In the extended transparent mode the EXMR register has to be set to 'xxx00000` 2.6.6 Timer The timer provides two modes (Table 35), a count down timer interrupt, i.e. an interrupt is generated only once after expiration of the selected period, and a periodic timer interrupt, which means an interrupt is generated continuously after every expiration of that period. * Table 35 Address 04H Timer Register TIMR Modes Periodic Count Down Period 64 ... 2048 ms 2.048 ... 14.336 s When the programmed period has expired an interrupt is generated (ISTA.TIN). The host controls the timer by setting bit CMDR.STI to start the timer and by writing register TIMR to stop the timer. After time period T1 an interrupt is generated continuously if CNT=7 or a single interrupt is generated after timer period T if CNT<7 (Figure 64). Data Sheet 135 2001-03-30 PEF 81912/81913 Functional Description * Retry Counter 0 ... 6 : Count Down Timer 7 : Periodic Timer T = CNT x 2.048 sec + T1 T = T1 Expiration Period T1 = (VALUE + 1) x 0.064 sec 76543210 TIMR1 CNT VALUE 24H 21150_14 Figure 64 Timer Register 2.6.7 HDLC Controller Interrupts All interrupt sources from the ISTAH register are combined (ORed) to a single HDLC controller interrupt signal hint. Each of the interrupt sources can individually be masked in the MASKH register. A masked interrupt is not indicated in the ISTAH register but remains internally stored and pending until the interrupt is unmasked and read by the host. The individual interrupt sources of the HDLC controller during reception and transmission of data are explained in Chapter 2.6.2.1 or Chapter 2.6.3.1 respectively. The HDLC controller interrupts XDU and XMR have a special impact on the internal functions. E.g. the transmitter of the HDLC controller is locked if a data underrun condition occurs and the ISTAH.XDU is not read (the interrupt can only be read if unmasked), same applies for XMR. Data Sheet 136 2001-03-30 PEF 81912/81913 Functional Description MASK U ST CIC TIN WOV S MOS HDLC ISTA U ST CIC TIN WOV S MOS HDLC MASKH RME RPF RFO XPR XMR XDU ISTAH RME RPF RFO XPR XMR XDU INT Figure 65 Interrupt Status Registers of the HDLC Controller 2.6.8 Test Function The Q-SMINT(R)IX provides test and diagnostic functions for the HDLC controller: Digital loop via TLP (Test Loop, TMH register) command bit (Figure 66): The TX path of the HDLC controller is still connected to IOM(R)-2 but it is internally connected with the RX path. All incoming data from the IOM(R)-2 is ignored. This is used for testing HDLC functionality excluding layer 1 (U-transceiver (loopback between XFIFO and RFIFO). * TMH:TLP = 0 IOM-2 Data Out Data In TMH:TLP = 1 IOM-2 Data Out Data In HDLC HDLC macro_8 Figure 66 Data Sheet Layer 2 Test Loops 137 2001-03-30 PEF 81912/81913 Functional Description 2.6.9 Reset Behavior After reset all pointers to the FIFOs are set to "0", the XPR interrupt is set to "1" but cannot be read by the host as it is masked, i.e. it must be unmasked so it can be read. Data Sheet 138 2001-03-30 PEF 81912/81913 Operational Description 3 3.1 3.1.1 Operational Description Layer 1 Activation/Deactivation Complete Activation Initiated by Exchange Figure 67 depicts the procedure if activation has been initiated by the exchange side (LT). * IOM(R)-2 TE S/T-Reference Point NT U-Reference Point LT IOM(R)-2 DC DI INFO 0 INFO 0 S0 DC DI C DC DI Uk0 SL0 SN0 TL DC DI AR PU DC1) SL0 TN SN1 SN0 SL1 SL2 (act = 0, dea = 1, uoa = 1) SN2 ARM AR AR AR INFO 2 AR AI AI AI AI INFO 4 AI AR8/10 SBCX-X or IPAC-X 1)C/I-Code SN3 (act = 0, sai = 0) UAI SN3 (act = 0, sai = 1) SL3T (act = 0, dea = 1, uoa = 1) SN3 (act = 1, sai = 1) SL3T (act = 1, dea = 1, uoa = 1) AI SN3T AR2) AR INFO 3 Q-SMINTIX DC is not issued in case of simplified state machine is selected 2) DFE-Q C/I-Code AR is optional ITD08687.vsd Figure 67 Complete Activation Initiated by Exchange Data Sheet 139 2001-03-30 PEF 81912/81913 Operational Description 3.1.2 * Complete Activation Initiated by TE Figure 68 depicts the procedure if activation has been initiated by the terminal side (TE). IOM(R)-2 TE S/T-Reference Point NT U-Reference Point LT IOM(R)-2 DC DI TIM PU AR INFO 0 INFO 0 S0 DC DI C DC DI Uk0 SL0 SN0 DC DI INFO 1 8ms TIM TIM PU AR AR DC1) TN SN1 SN0 SL1 SL2 (act = 0, dea = 1, uoa = 0) SN2 SN3 (act = 0, sai = 1) ARM AR RSY AR INFO 2 INFO 0 INFO 3 AR AR SL3T (uoa = 1) UAI AI AI AI SN3 (act = 1, sai = 1) SL3T (act = 1, dea = 1, uoa = 1) SN3T AI AI SBCX-X or IPAC-X INFO 4 AI Q-SMINTIX 1)C/I-Code DFE-Q DC is not issued in case of simplified state machine is selected ITD08688.vsd Figure 68 Complete Activation Initiated by TE Data Sheet 140 2001-03-30 PEF 81912/81913 Operational Description 3.1.3 Complete Activation Initiated by NT Figure 69 depicts the procedure if activation has been initiated by the Q-SMINT(R)IX itself (e.g. after hook-off of a local analog phone). * IOM(R)-2 TE S/T-Reference Point NT U-Reference Point LT IOM(R)-2 DC DI INFO 0 INFO 0 S0 DC DI C DC DI TIM PU AR Uk0 SL0 SN0 DC DI TN DC1) SN1 SN0 SL1 SL2 (act = 0, dea = 1, uoa = 0) SN2 SN3 (act = 0, sai = 1) SL3T (uoa = 1) AR AR INFO 2 AR INFO 3 AI AR AI SN3 (act = 1, sai = 1) SL3T (act = 1, dea = 1, uoa = 1) AI AI INFO 4 AI SBCX-X or IPAC-X 1)C/I-Code AR ARM UAI AI SN3T Q-SMINTIX DC is not issued in case of simplified state machine is selected DFE-Q ITD08689.vsd Figure 69 Complete Activation Initiated by Q-SMINT(R)IX Data Sheet 141 2001-03-30 PEF 81912/81913 Operational Description 3.1.4 Complete Deactivation Figure 70 depicts the procedure if deactivation has been initiated. Deactivation of layer 1 is always initiated by the exchange. * IOM(R)-2 TE S/T-Reference Point NT U-Reference Point LT IOM(R)-2 AI (AR) INFO 4 INFO 3 S0 AI AI C AI AI Uk0 SL3T (act = 1, dea = 1, uoa = 1) SN3T (act = 1, dea = 1) AR AI DR DC1) 2) DR DR INFO 0 RSY DR DI DC INFO 0 DI DC DI DC SBCX-X or IPAC-X & TIM 3 ms SL3T (act = 0, dea = 0) SL0 SL0 40 ms DEAC DI DC DFE-Q Q-SMINTIX 1)C/I-Code 2) DR is issued in case of simplified state machine is selected C/I-Code AR might be issued before C/I-Code DC in case of M4 Validation Algorithm TLL, CRC&TLL or On Change is selected ITD08690.vsd Figure 70 Complete Deactivation Initiated by Exchange Data Sheet 142 2001-03-30 PEF 81912/81913 Operational Description 3.1.5 * Loop 2 Figure 71 depicts the procedure if loop 2 is closed and opened. IOM(R)-2 S/T-Reference Point IOM(R)-2 AI AR8/10 TE INFO 4 INFO 3 S0 AI AI NT U-Reference Point LT C AI AI Uk0 SL3T (act = 1, dea = 1, uoa = 1) SN3T (act = 1, dea = 1) AR AI 2B+D EOC: LBBD: act = 1 AIL AIL ISTAU.EOC=1 MON0:LBBD 2B+D EOC: RTN: act = 1 AI AI ISTAU.EOC=1 MON0:RTN 2B+D SBCX-X or IPAC-X Q-SMINTIX DFE-Q ITD10034.vsd Figure 71 Loop 2 Data Sheet 143 2001-03-30 PEF 81912/81913 Operational Description 3.2 Layer 1 Loopbacks Test loopbacks are specified by the national PTTs in order to facilitate the location of defect systems. Four different loopbacks are defined. The position of each loopback is illustrated in Figure 72. * U S-BUS Loop 2 S-Transceiver U IOM(R)-2 Loop 2 U-Transceiver IOM(R)-2 Loop 1 A U-Transceiver U-Transceiver Loop 1 U-Transceiver NT IOM(R)-2 Loop 2 Layer-1 Controller U-Transceiver IOM(R)-2 Repeater (optional) Exchange IOM-2 Loop 3 Layer-1 Controller U-Transceiver PBX or TE loop_2b1q.emf Figure 72 Test Loopbacks Loopbacks #1, #1A and #2 are controlled by the exchange. Loopback #3 is controlled locally on the remote side. All four loopback types are transparent. This means all bits that are looped back will also be passed onwards in the normal manner. Only the data looped back internally is processed; signals on the receive pins are ignored. The propagation delay of actually looped B and D channels data must be identical in all loopbacks. Besides the remote controlled loopback stimulation via the EOC channel, the QSMINT(R)IX features also direct loopback control via its register set. 3.2.1 Analog Loopback U-Transceiver (No. 3) Loopback #3 is closed by the U-transceiver as near to the U-interface as possible, i.e. the loop is closed in the analog part by short circuiting the output to the input. The signal on the line is ignored in this state. For this reason it is also called analog loopback. All analog signals will still be passed on to the U-interface. Before an analog loopback is closed by the appropriate C/I-command ARL (activation request loopback 3), the U-transceiver shall have been reset. Data Sheet 144 2001-03-30 PEF 81912/81913 Operational Description In order to open an analog loopback correctly, force the U-transceiver into the RESET state. This ensures that the echo coefficients and equalizer coefficients will converge correctly when activating anew. 3.2.2 Analog Loop-Back S-Transceiver The Q-SMINT(R)IX provides test and diagnostic functions for the S/T interface: The internal local loop (internal Loop A) is activated by a C/I command ARL or by setting the bit LP_A (Loop Analog) in the S_CMD register if the layer-1 statemachine is disabled. The transmit data of the transmitter is looped back internally to the receiver. The data of the IOM(R)-2 input B- and D-channels are looped back to the output B- and D-channels. The S/T interface level detector is enabled, i.e. if a level is detected this will be reported by the Resynchronization Indication (RSY) but the loop function is not affected. Depending on the DIS_TX bit in the S_CONF2 register the internal local loop can be transparent or non transparent to the S/T line. The external local loop (external Loop A) is activated in the same way as the internal local loop described above. Additionally the EXLP bit in the S_CONF0 register has to be programmed and the loop has to be closed externally as described in Figure 73. The S/T interface level detector is disabled. * SX1 100 SX2 SCOUT-S(X) SR1 100 SR2 Figure 73 External Loop at the S/T-Interface Data Sheet 145 2001-03-30 PEF 81912/81913 Operational Description 3.2.3 Loopback No.2 For loopback #2 several alternatives exist. Both the type of loopback and the location may vary. The following loopback types belong to the loopback-#2 category: * * * * complete loopback (B1,B2,D), in the U-transceiver complete loopback (B1,B2,D), in a downstream device B1-channel loopback, always performed in the U-transceiver B2-channel loopback, always performed in the U-transceiver All loop variations performed by the U-transceiver are closed as near to the internal IOM(R)-2 interface as possible. Normally loopback #2 is controlled by the exchange. The maintenance channel is used for this purpose. All loopback functions are latched. This allows channel B1 and channel B2 to be looped back simultaneously. 3.2.3.1 Complete Loopback When receiving the request for a complete loopback, the U transceiver passes it on to the downstream device, e.g. the S-bus transceiver. This is achieved by issuing the C/Icode AIL in the "Transparent" state or C/I = ARL in states different than "Transparent" (note: this holds true only for the EOC automode). The U transceiver may be commanded to close the complete loopback itself. Figure 74 illustrates the two options. * S-Transceiver 2B+D loop request U-Transceiver 2 B+D U loop command Controller loop command lp2bymon8.vsd Figure 74 Complete Loopback Options in NT-Mode The complete loopback is either opened under control of the exchange via the maintenance channel or locally controlled via the C. No reset is required for loopback #2. The line stays active and is ready for data transmission. Data Sheet 146 2001-03-30 PEF 81912/81913 Operational Description 3.2.3.2 Loopback No.2 - Single Channel Loopbacks Single channel loopbacks are always performed directly in the U-Transceiver. No difference between the B1-channel and the B2-channel loopback control procedure exists. 3.2.4 Local Loopbacks Featured By the LOOP Register Besides the standardized remote loopbacks the U-transceiver features additional local loopbacks for enhanced test and debugging facilities. The local loopbacks that are featured by register LOOP are shown in Figure 75. They are closed in the U-transceiver itself and can be activated regardless of the current operational status. By the LOOP register it can be configured whether the loopback is closed only for the B1 and/or B2 or for 2B+D channels and whether the loopback is closed towards the internal IOM(R)-2 interface or towards the U-Interface. By default the loopbacks are set to transparent mode. In transparent mode the data is both passed on and looped back. In non-transparent mode the data is not forwarded but substituted by 1s (idle code). Besides the loopbacks in the system interface an additional digital loopback (DLB), the Framer/ Deframer loopback, is featured. It allows to test most digital functions of the Utransceiver besides the signal processing blocks. Data Sheet 147 2001-03-30 PEF 81912/81913 Operational Description * LOOP.LB1=1 LOOP.LB2=1 LOOP.LBBD= 1 & LOOP.U/IOM= 1 LOOP.LB1=1 LOOP.LB2=1 LOOP.LBBD= 1 & LOOP.U/IOM= 0 Analog Part Line Interface Unit Digital Part DAC Echo Canceller ADC PDM Filter 2B1Q Scrambler UFraming Tx-FIFO + Timing Recovery A G C Rx-FIFO Equalizer 2B1Q DeScrambler U-DeFraming IOM-2 Interface Bandgap, Bias, Refer. U-Transceiver Activation/ Deactivation Controller LOOP.DLB= 1 Analog Part Line Interface Unit DAC Digital Part 2B1Q Echo Canceller Scrambler UFraming Tx-FIFO ADC PDM Filter + Timing Recovery A G C Equalizer 2B1Q DeScrambler U-DeFraming Rx-FIFO IOM-2 Interface Bandgap, Bias, Refer. U-Transceiver Activation/ Deactivation Controller loopreg.emf Figure 75 Data Sheet Loopbacks Featured by Register LOOP 148 2001-03-30 PEF 81912/81913 Operational Description 3.3 3.3.1 * External Circuitry Power Supply Blocking Recommendation The following blocking circuitry is suggested. VDDa_UR VDDa_UX VDDa_SR VDDa_SX VDDD VDDD 100nF 1) 3.3V 100nF 1) 100nF 1) 100nF 1) 100nF 1) 100nF 1) 1F VSSD VSSD GND VSSa_SX VSSa_SR VSSa_UX VSSa_UR 1) These capacitors should be located as near to the pins as possible blocking_caps_Smint.vsd Figure 76 Power Supply Blocking 3.3.2 U-Transceiver The Q-SMINT(R)IX is connected to the twisted pair via a transformer. Figure 77 shows the recommended external circuitry. The recommended protection circuitry is not displayed. Note: The integrated hybrid as specified for Version 1.1 is no more available in Version 1.3 and an external hybrid is required. Data Sheet 149 2001-03-30 PEF 81912/81913 Operational Description *. AOUT R3 RT n BIN R4 RCOMP RPTC C AIN >1 Loop R4 RCOMP RPTC R3 extcirc_U_Q2_exthybrid.emf BOUT RT Figure 77 External Circuitry U-Transceiver U-Transformer Parameters The following Table 36 lists parameters of typical U-transformers: Table 36 U-Transformer Parameters Symbol Value n LH 1:2 14.5 <75 100 2.51) 5 1) U-Transformer Parameters U-Transformer ratio; Device side : Line side Main inductance of windings on the line side Unit mH H pF Leakage inductance of windings on the line side LS Coupling capacitance between the windings on CK the device side and the windings on the line side DC resistance of the windings on device side DC resistance of the windings on line side 1) RB RL RB / RL according to equation[2] Data Sheet 150 2001-03-30 PEF 81912/81913 Operational Description Resistors of the External Hybrid R3, R4 and RT R3 = 1.3 k R4 = 1.0 k RT = 9.5 Resistors on the Line Side RPTC / Chip Side RT Optional use of up to 2x20 resistors (2xRPTC) on the line side of the transformer requires compensation resistors RCOMP depending on RPTC: 2RPTC + 8RCOMP = 40 2RPTC + 4(2RCOMP + 2RT + ROUT + RB) + RL = 135 RB, RL : see Table 36 ROUT : see Table 43 27 nF Capacitor C To achieve optimum performance the 27 nF capacitor should be MKT. A Ceramic capacitor is not recommended. Tolerances * Rs: 1% * C=27 nF: 10-20% * L=14.5 mH: 10% (1) (2) 3.3.3 S-Transceiver In order to comply to the physical requirements of ITU recommendation I.430 and considering the national requirements concerning overvoltage protection and electromagnetic compatibility (EMC), the S-transceiver needs some additional circuitry. S-Transformer Parameters The following Table 37 lists parameters of a typical S-transformer: Data Sheet 151 2001-03-30 PEF 81912/81913 Operational Description Table 37 S-Transformer Parameters Symbol Value n LH 2:1 typ. 30 typ. <3 typ. <100 typ. 2.4 typ. 1.4 mH H pF Unit Transformer Parameters Transformer ratio; Device side : Line side Main inductance of windings on the line side Leakage inductance of windings on the line side LS Coupling capacitance between the windings on CK the device side and the windings on the line side DC resistance of the windings on device side DC resistance of the windings on line side Transmitter RB RL The transmitter requires external resistors Rstx = 47 in order to adjust the output voltage to the pulse mask (nominal 750 mV according to ITU I.430, to be tested with the test mode "TM1") on the one hand and in order to meet the output impedance of minimum 20 on the other hand (to be tested with the testmode 'Continuous Pulses') on the other hand. Note: The resistance of the S-transformer must be taken into account when dimensioning the external resistors Rstx. If the transmit path contains additional components (e.g. a choke), then the resistance of these additional components must be taken into account, too. * 47 SX1 20...40 VDD 2:1 GND SX2 47 DC Point extcirc_S.vsd Figure 78 External Circuitry S-Interface Transmitter Data Sheet 152 2001-03-30 PEF 81912/81913 Operational Description Receiver The receiver of the S-transceiver is symmetrical. 10 k overall resistance are recommended in each receive path. It is preferable to split the resistance into two resistors for each line. This allows to place a high resistance between the transformer and the diode protection circuit (required to pass 96 kHz input impedance test of ITU I.430 [8] and ETS 300012-1). The remaining resistance (1.8 k) protects the Stransceiver itself from input current peaks. * 1k8 SR1 VDD 8k2 2:1 GND SR2 1k8 8k2 DC Point extcirc_S.vsd Figure 79 External Circuitry S-Interface Receiver 3.3.4 Oscillator Circuitry Figure 80 illustrates the recommended oscillator circuit. * CLD XOUT 15.36 MHz XIN CLD Figure 80 Crystal Oscillator Data Sheet 153 2001-03-30 PEF 81912/81913 Operational Description Table 38 Parameter Frequency Frequency calibration tolerance Load capacitance Max. resonance resistance Max. shunt capacitance Oscillator mode External Components and Parasitics The load capacitance CL is computed from the external capacitances CLD, the parasitic capacitances CPar (pin and PCB capacitances to ground and VDD) and the stray capacitance CIO between XIN and XOUT: ( C LD + C Par ) x ( C LD + C Par ) C L = ------------------------------------------------------------------------ + CIO ( C LD + C Par ) + ( C LD + C Par ) For a specific crystal the total load capacitance is predefined, so the equation must be solved for the external capacitances CLD, which is usually the only variable to be determined by the circuit designer. Typical values for the capacitances CLD connected to the crystal are 22 - 33 pF. CL R1 C0 Crystal Parameters Symbol f Limit Values 15.36 +/-60 20 20 7 fundamental Unit MHz ppm pF pF 3.3.5 General * low power LEDs * MLT input supports - APC13112 - AT&T LH1465AB - discrete as proposed by Infineon Data Sheet 154 2001-03-30 PEF 81912/81913 Register Description 4 4.1 Register Description Address Space 7DH U-Transceiver 60H 5CH 40H 3CH 30H 20H Monitor Handler IOM(R)-2 Handler (CDA, TSDP, CR, STI) Interrupt, Global Registers S-Transceiver HDLC Controller, CI Reg. HDLC RFIFO/XFIFO 00H Figure 81 Address Space Data Sheet 155 2001-03-30 PEF 81912/81913 Register Description 4.2 Interrupts Special events in the Q-SMINT(R)IX are indicated by means of a single interrupt output, which requests the host to read status information from the Q-SMINT(R)IX or transfer data from/to the Q-SMINT(R)IX. Since only one INT request output is provided, the cause of an interrupt must be determined by the host reading the interrupt status registers of the Q-SMINT(R)IX. The structure of the interrupt status registers is shown in Figure 82. MASKU MLT CI FE/NEBE ISTAU MLT CI FE/NEBE M56 M4 EOC 6ms 12ms MASK U ST CIC TIN WOV S MOS HDLC ISTA U ST CIC TIN WOV S MOS HDLC M56 M4 EOC 6ms 12ms MSTI STOV21 STOV20 STOV11 STOV10 STI21 STI20 STI11 STI10 STI STOV21 STOV20 STOV11 STOV10 STI21 STI20 STI11 STI10 MASKS LD RIC SQC SQW MRE ASTI ACK21 ACK20 ACK11 ACK10 ISTAS LD RIC SQC SQW MDR MER MDA MAB MOSR CI1E CIX1 CIC0 CIC1 CIR0 INT RME RPF RFO XPR XMR XDU MASKH RME RPF RFO XPR XMR XDU ISTAH MIE MOCR Figure 82 Q-SMINT(R)IX Interrupt Status Registers Data Sheet 156 2001-03-30 PEF 81912/81913 Register Description After the Q-SMINT(R)IX has requested an interrupt by setting its INT pin to low, the host must read first the Q-SMINT(R)IX interrupt status register (ISTA) in the associated interrupt service routine. The INT pin of the Q-SMINT(R)IX remains active until all interrupt sources are cleared. Therefore, it is possible that the INT pin is still active when the interrupt service routine is finished. Each interrupt indication of the interrupt status registers can selectively be masked by setting the respective bit in the MASK register. For some interrupt controllers or hosts it might be necessary to generate a new edge on the interrupt line to recognize pending interrupts. This can be done by masking all interrupts at the end of the interrupt service routine (writing FFH into the MASK register) and writing back the old mask to the MASK register. Data Sheet 157 2001-03-30 PEF 81912/81913 Register Description 4.3 Register Summary r(0) = reserved, implemented as zero. HDLC Control Registers, CI Handler Name RFIFO 7 6 5 4 3 2 1 0 ADDR R/W RES 00H1FH 00H1FH r(0) 0 XACI XME DIM1 r(0) r(0) 0 r(0) XRES DIM0 ITF 20H 20H 21H 21H R D-Channel Receive FIFO XFIFO D-Channel Transmit FIFO W ISTAH MASKH STAR CMDR MODEH EXMR TIMR SAP1 SAP2 RBCL RBCH TEI1 TEI2 RSTA TMH RME RME XDOV RMC RPF RPF XFW RRES RFO RFO r(0) 0 XPR XPR r(0) STI r(0) SRA XMR XMR RACI XTF RAC XCRC XDU XDU r(0) 0 DIM2 RCRC VALUE R 10H W FCH R W 40H 00H MDS2 MDS1 MDS0 XFBS RFBS CNT 22H R/W C0H 23H R/W 00H 24H R/W 00H SAPI1 SAPI2 RBC7 r(0) r(0) r(0) OV TEI1 TEI2 VFR r(0) RDO r(0) CRC r(0) RAB r(0) SA1 r(0) SA0 r(0) RBC11 0 0 MHA MLA RBC0 RBC8 EA1 EA1 25H 26H 26H 27H 27H 28H 28H 29H 2AH2DH W FCH W FCH R R W W R 00H 00H FFH FFH 0FH C/R r(0) TA TLP R/W 00H reserved Data Sheet 158 2001-03-30 PEF 81912/81913 Register Description CIR0 CIX0 CIR1 CIX1 CODR0 CODX0 CODR1 CODX1 CIC0 TBA2 CIC1 TBA1 S/G TBA0 CICW CICW BAS BAC CI1E CI1E 2EH 2EH 2FH 2FH R W R W F3H FEH FEH FEH Data Sheet 159 2001-03-30 PEF 81912/81913 Register Description S-Transceiver Name S_ CONF0 7 DIS_ TR 6 BUS 5 EN_ ICV 4 0 3 L1SW 2 0 1 EXLP 0 0 ADDR R/W RES 30H 31H 0 0 0 32H 33H 34H 35H 35H 36H-37H RIC RIC SQC SQC MODE2-0 SQW SQW 38H 39H 3AH 3BH R 00H R/W 80H R 00H R/W 40H reserved S_ CONF2 S_STA S_CMD SQRR SQXR DIS_ TX RINF XINF MSYN MFEN 0 MFEN 0 0 0 0 0 0 0 ICV DPRIO 0 0 0 1 SQR1 SQX1 FSYN PD SQR2 SQX2 0 LP_A SQR3 SQX3 LD 0 SQR4 SQX4 R/W 08H R W 00H 00H reserved ISTAS MASKS S_ MODE 0 1 0 x 1 0 x 1 0 x 1 0 LD LD DCH_ INH R/W FFH R/W 02H reserved Data Sheet 160 2001-03-30 PEF 81912/81913 Register Description Interrupt, General Configuration Name ISTA MASK MODE1 MODE2 ID SRES 7 U U 6 ST ST MCLK LED2 0 0 LED1 0 0 RES_ CI/TIC 0 5 CIC CIC CDS LEDC 4 TIN TIN WTC1 0 3 WOV WOV WTC2 0 2 S S CFS 0 1 MOS MOS RSS2 0 HDLC HDLC RSS1 ADDR R/W RES 3CH 3CH 3DH 3EH 3FH RES_ S RES_ U 3FH R W 00H FFH R/W 04H R/W 00H R W 01H 00H AMOD PPSDX DESIGN RES_ HDLC 0 Data Sheet 161 2001-03-30 PEF 81912/81913 Register Description IOM Handler (Timeslot, Data Port Selection, CDA Data and CDA Control Register) Name CDA10 CDA11 CDA20 CDA21 CDA_ TSDP10 CDA_ TSDP11 CDA_ TSDP20 CDA_ TSDP21 DPS 0 7 6 5 4 3 2 1 0 ADDR R/W RES 40H 41H 42H 43H 44H 45H 46H 47H 48H4BH TSS 4CH R/W 84H R/W FFH R/W FFH R/W FFH R/W FFH R/W 00H R/W 01H R/W 80H R/W 81H Controller Data Access Register Controller Data Access Register Controller Data Access Register Controller Data Access Register 0 0 TSS DPS 0 0 0 TSS DPS 0 0 0 TSS DPS 0 0 0 TSS reserved S_ TSDP_ B1 S_ TSDP_ B2 CDA1_ CR CDA2_ CR DPS 0 0 0 DPS 0 0 0 TSS 4DH R/W 85H 0 0 EN_ TBM EN_ TBM EN_I1 EN_I0 EN_O1 EN_O0 SWAP 4EH 4FH R/W 00H R/W 00H 0 0 EN_I1 EN_I0 EN_O1 EN_O0 SWAP Data Sheet 162 2001-03-30 PEF 81912/81913 Register Description IOM Handler (Control Registers, Synchronous Transfer Interrupt Control) Name 7 6 5 4 3 2 1 0 ADDR R/W RES 50H EN_ B2X DPS_ H 0 EN_ B1X D_CS 51H 52H 53H 54H 55H DIS_ IOM 56H 57H 58H 58H 59H 5AH5BH R/W FFH R/W 04H R/W 40H R/W 00H R/W 00H R/W 08H R R FFH 00H 00H reserved S_CR 1 CI_CS EN_ D EN_D EN_ B2R EN_ B2H 0 EN_ B1R EN_ B1H 0 HCI_CR DPS_ CI1 DPS EN_ CI1 EN_ MON HCS MON_ CR SDS1_ CR SDS2_ CR IOM_CR 0 MCS ENS_ TSS ENS_ TSS SPU ENS_ ENS_ TSS+1 TSS+3 ENS_ ENS_ TSS+1 TSS+3 0 0 0 TSS 0 TSS TIC_ DIS EN_ BCL 0 DIS_ OD MCDA STI MCDA21 STOV 21 0 STOV 20 0 MCDA20 STOV 11 0 STOV 10 0 MCDA11 STI 21 ACK 21 STI 21 STI 20 ACK 20 STI 20 MCDA10 STI 11 ACK 11 STI 11 STI 10 ACK 10 STI 10 ASTI W MSTI STOV 21 STOV 20 STOV 11 STOV 10 R/W FFH reserved Data Sheet 163 2001-03-30 PEF 81912/81913 Register Description MONITOR Handler Name MOR MOX MOSR MOCR MSTA MCONF MDR MRE 0 0 MER MRC 0 0 7 6 5 4 3 2 1 0 ADDR R/W RES 5CH 5CH 0 0 0 0 0 0 TOUT TOUT 5DH 5EH 5FH 5FH R W R FFH FFH 00H MONITOR Receive Data MONITOR Transmit Data MDA MIE 0 0 MAB MXC 0 0 0 0 0 0 0 0 MAC 0 R/W 00H R W 00H 00H Data Sheet 164 2001-03-30 PEF 81912/81913 Register Description Register Summary U-Transceiver Name OPMODE 7 0 6 UCI 5 FEBE 4 MLT 3 0 2 CI_ SEL 1 0 0 0 ADDR R/W RES 60H R*/W 14H MFILT M56 FILTER M4 FILTER reserved EOC FILTER 61H 62H R*/W 14H EOCR 0 i1 0 i2 0 i2 0 i3 0 i3 0 i4 0 i4 a1 i5 a1 i5 a2 i6 a2 i6 a3 i7 a3 i7 d/m i8 d/m i8 63H 64H 65H 66H 67H 68H 69H 6AH R 0FH FFH EOCW 0 i1 W 01H 00H M4RMASK M4WMASK M4R M4W M56R M56W UCIR UCIW TEST 0 1 0 0 0 M4 Read Mask Bits M4 Write Mask Bits verified M4 bit data of last received superframe M4 bit data to be send with next superframe MS2 1 0 0 0 MS1 1 0 0 0 NEBE 1 0 0 0 CCRC M61 M61 M52 M52 M51 M51 FEBE FEBE R*/W 00H R*/W A8H R BEH R*/W BEH R W R W 1FH FFH 00H 01H 6BH 6CH 6DH 6EH C/I code output C/I code input +-1 Tones LBBD 0 40 KHz LB1 6FH R*/W 00H LOOP FEBE NEBE 0 DLB TRANS U/IOM 1 LB2 70H 71H 72H 73H79H R*/W 08H R R 00H 00H FEBE Counter Value NEBE Counter Value reserved Data Sheet 165 2001-03-30 PEF 81912/81913 Register Description ISTAU MLT CI FEBE/ NEBE MASKU MLT CI FEBE/ NEBE reserved FW_ VERSION M56 M4 EOC 6ms 12ms 7AH R 00H M56 M4 EOC 6ms 12ms 7BH R*/W FFH 7CH 7DH 7EH7FH R 6xH FW Version Number reserved *) read back function for test use Note: Registers, which are denoted as `reserved`, may not be accessed by the C, neither for read nor for write operations. 4.4 Reset of U-Transceiver Functions During Deactivation or with C/I-Code RESET The following U-transceiver registers are reset during deactivation or with software reset: Table 39 Register EOCR EOCW M4R M4W M56R M56W TEST LOOP Reset of U-Transceiver Functions During Deactivation or with C/ICode RESET Reset to 0FFFH 0100H BEH BEH 1FH FFH Affected Bits all bits all bits all bits all bits all bits are reset besides MS2 and MS1 all bits only bit CCRC is reset only the bits LBBD, LB2 and LB1 are reset Data Sheet 166 2001-03-30 PEF 81912/81913 Register Description 4.5 U-Transceiver Mode Register Evaluation Timing The point of time when mode settings are detected and executed differs with the mode register type. Two different behaviors can be classified: * evaluation and execution after SW-reset (C/I= RES) or upon transition out of state 'Deactivated' Note: Write access to these registers/bits is allowed only, while the state machine is in state Reset or Deactivated. * immediate evaluation and execution Below the mode registers are listed and grouped according to the different evaluation times as stated above. Table 40 Register U-Transceiver Mode Register Evaluation Timing Affected Bits Registers Evaluated After SW-Reset or Upon Transition Out of State Deactivated OPMODE MFILT bit UCI, MLT complete register Immediate Evaluation and Execution OPMODE M4RMASK M4WMASK TEST LOOP MASKU bit FEBE, CI_SEL complete register complete register complete register complete register complete register Data Sheet 167 2001-03-30 PEF 81912/81913 Register Description 4.6 4.6.1 RFIFO 7 Detailed HDLC Control and C/I Registers RFIFO - Receive FIFO read Address: 00-1FH 0 Receive data The RFIFO contains up to 32 bytes of received data. After an ISTAH.RPF interrupt, a complete data block is available. The block size can be 4, 8, 16, 32 bytes depending on the EXMR.RFBS setting. After an ISTAH.RME interrupt, the number of received bytes can be obtained by reading the RBCL register. A read access to any address within the range 00H-1FH gives access to the "current" FIFO location selected by an internal pointer which is automatically incremented after each read access. This allows for the use of efficient "move string" type commands by the microcontroller. 4.6.2 XFIFO 7 XFIFO - Transmit FIFO write Address: 00-1FH 0 Transmit data Depending on EXMR.XFBS up to 16 or 32 bytes of transmit data can be written to the XFIFO following an ISTAH.XPR interrupt. A write access to any address within the range 00-1FH gives access to the "current" FIFO location selected by an internal pointer which is automatically incremented after each write access. This allows the use of efficient "move string" type commands by the microcontroller. Data Sheet 168 2001-03-30 PEF 81912/81913 Register Description 4.6.3 ISTAH ISTAH - Interrupt Status Register HDLC read Address: 20H Value after reset: 10H Note: The reset value cannot be read right after reset as all interrupts are masked, i.e. the XPR interrupt remains internally stored and can only be read as soon as the corresponding mask bit is set to "0". 7 RME 6 RPF 5 RFO 4 XPR 3 XMR 2 XDU 1 r(0) 0 r(0) RME Receive Message End 0= 1= inactive One complete frame of length less than or equal to the defined block size (EXMR.RFBS) or the last part of a frame of length greater than the defined block size has been received. The contents are available in the RFIFO. The message length and additional information may be obtained from RBCH and RBCL and the RSTA register. RPF Receive Full 0= 1= inactive A data block of a frame longer than the defined block size (EXMR.RFBS) has been received and is available in the RFIFO. The frame is not yet complete. RFO Receive Frame Overflow 0= 1= inactive The received data of a frame could not be stored, because the RFIFO is occupied. The whole message is lost. This interrupt can be used for statistical purposes and indicates that the microcontroller does not respond quickly enough to a RPF or RME interrupt (ISTAH). XPR Transmit Pool Ready 0= inactive 169 2001-03-30 Data Sheet PEF 81912/81913 Register Description 1= A data block of up to the defined block size (EXMR.XFBS) can be written to the XFIFO. A XPR interrupt will be generated in the following cases: * after a XTF or XME command as soon as the 16 / 32 bytes in the XFIFO are available and the frame is not yet complete. * after a XTF together with a XME command is issued, when the whole frame has been transmitted. * after reset * after XRES XMR Transmit Message Repeat 0= 1= inactive The transmission of the last frame has to be repeated because a collision on the S bus has been detected after the 16th/32nd data byte of a transmit frame. If a XMR interrupt occurs the transmit FIFO is locked until the XMR interrupt is read by the host (interrupt cannot be read if masked in MASKH). XDU Transmit Data Underrun 0= 1= inactive The current transmission of a frame is aborted by transmitting seven `1's because the XFIFO holds no further data. This interrupt occurs whenever the microcontroller has failed to respond to a XPR interrupt (ISTAH register) quick enough, after having initiated a transmission and the message to be transmitted is not yet complete. If a XMR interrupt occurs the transmit FIFO is locked until the XDU interrupt is read by the host (interrupt cannot be read if masked in MASKH). Data Sheet 170 2001-03-30 PEF 81912/81913 Register Description 4.6.4 MASKH MASKH - Mask Register HDLC write Address: 20H Value after reset: FCH 7 RME 6 RPF 5 RFO 4 XPR 3 XMR 2 XDU 1 0 0 0 Each interrupt source in the ISTAH register can be selectively masked by setting the corresponding bit in MASKH to `1'. Masked interrupt status bits are not indicated when ISTAH is read. Instead, they remain internally stored and pending, until the mask bit is reset to `0'. Bit 0..7 Mask Bits 0= 1= interrupt active interrupt masked 4.6.5 STAR STAR - Status Register read Address: 21H Value after reset: 40H 7 XDOV 6 XFW 5 r(0) 4 r(0) 3 RACI 2 r(0) 1 XACI 0 0 XDOV Transmit Data Overflow 0= 1= No transmit data overflow More than the selected block size of 16 or 32 bytes have been written into the XFIFO, i.e. data has been overwritten. XFW Transmit FIFO Write Enable 0= Data can not be written in the XFIFO Data Sheet 171 2001-03-30 PEF 81912/81913 Register Description 1= Data can be written in the XFIFO. This bit may be polled instead of (or in addition to) using the XPR interrupt. RACI Receiver Active Indication 0= 1= The HDLC receiver is not active The HDLC receiver is active when RACI = `1'. This bit may be polled. The RACI bit is set active after a begin flag has been received and is reset after receiving an abort sequence. The HDLC-transmitter is not active The HDLC-transmitter is active when XACI = `1'. This bit may be polled. The XACI-bit is active when a XTF-command is issued and the frame has not been completely transmitted. XACI Transmitter Active Indication 0= 1= 4.6.6 CMDR CMDR - Command Register write Address: 21H Value after reset: 00H 7 RMC 6 RRES 5 0 4 STI 3 XTF 2 0 1 XME 0 XRES RMC Receive Message Complete 0= 1= inactive Reaction to RPF (Receive Pool Full) or RME (Receive Message End) interrupt. By setting this bit, the microcontroller confirms that it has fetched the data, and indicates that the corresponding space in the RFIFO may be released. RRES Receiver Reset 0= 1= inactive HDLC receiver is reset, the RFIFO is cleared of any data. STI Start Timer 0= inactive 172 2001-03-30 Data Sheet PEF 81912/81913 Register Description 1= XTF The Q-SMINT(R)IX hardware timer is started (see TIMR register). Transmit Transparent Frame 0= 1= inactive After having written up to 16 or 32 bytes (EXMR.XFBS) in the XFIFO, the microcontroller initiates the transmission of a transparent frame by setting this bit to `1'. The opening flag is automatically added to the message by the Q-SMINT(R)IX except in the extended transparent mode. XME Transmit Message End 0= 1= inactive By setting this bit to `1' the microcontroller indicates that the data block written last in the XFIFO completes the corresponding frame. The Q-SMINT(R)IX completes the transmission by appending the CRC (if XCRC = 0) and the closing flag sequence to the data except in the extended transparent mode. XRES Transmitter Reset 0= 1= inactive HDLC transmitter is reset and the XFIFO is cleared of any data. This command can be used by the microcontroller to abort a frame currently in transmission. All of these bits must not be set twice within one BCL clock cycle. Note: After a XPR interrupt further data has to be written to the XFIFO and the appropriate Transmit Command (XTF) has to be written to the CMDR register again to continue transmission, when the current frame is not yet complete (see also XPR in ISTAH). During frame transmission, the 0-bit insertion according to the HDLC bit-stuffing mechanism is done automatically except in extended transparent mode. Data Sheet 173 2001-03-30 PEF 81912/81913 Register Description 4.6.7 MODEH MODEH - Mode Register HDLC Controller read/write Address: 22H Value after reset: C0H 7 MDS2 MDS1 MDS0 r(0) RAC DIM2 DIM1 0 DIM0 MDS2-0 Mode Select Determines the message transfer mode of the HDLC controller, as follows : MDS2-0 Mode Address Comparison 1.Byte 0 0 0 0 1 0 0 1 1 0 0 Reserved 1 Reserved 0 Non-Auto mode/8 - - TEI1,TEI2 Remark 2.Byte - - - - - One-byte address compare. 1 Non-Auto mode/16 SAP1,SAP2, TEI1,TEI2, Two-byte address SAPG TEIG compare. - - - 0 Extended transparent mode 1 1 0 Transparent - mode 0 - No address compare. All frames accepted. High-byte address compare. 1 1 1 0 1 Transparent SAP1,SAP2, - mode 1 mode 2 SAPG 1 Transparent - TEI1,TEI2, Low-byte address TEIG compare. Data Sheet 174 2001-03-30 PEF 81912/81913 Register Description Note: SAP1, SAP2: two programmable address values for the first received address byte (in the case of an address field longer than 1 byte); SAPG = fixed value FC / FEH. TEI1, TEI2: two programmable address values for the second (or the only, in the case of a one-byte address) received address byte; TEIG = fixed value FFH. Two different methods of the high byte and/or low byte address comparison can be selected by setting SAP1.MHA and/or SAP2.MLA (see also description of these bits in Chapter 4.6.10 or Chapter 4.6.11 respectively). RAC Receiver Active 0= 1= DIM2-0 The HDLC data is not evaluated in the receiver The HDLC receiver is activated Digital Interface Modes These bits define the characteristics of the IOM Data Ports (DU, DD). The DIM0 bit enables/disables the stop/go bit (S/G) evaluation. The DIM1 bit enables/disables the TIC bus access. The effect of the individual DIM bits is as follows: 0-0 = 0-1 = 00- = 01- = 1xx = Stop/go bit evaluation is disabled Stop/go bit evaluation is enabled TIC bus access is enabled TIC bus access is disabled Reserved 4.6.8 EXMR EXMR - Extended Mode Register read/write Address: 23H Value after reset: 00H 7 XFBS RFBS SRA XCRC RCRC r(0) 0 ITF XFBS Transmit FIFO Block Size 0= Block size for the transmit FIFO data is 32 byte Data Sheet 175 2001-03-30 PEF 81912/81913 Register Description 1= Block size for the transmit FIFO data is 16 byte Note: A change of XFBS will take effect after a transmitter command (CMDR.XME, CMDR.XRES, CMDR.XTF) has been written. RFBS Receive FIFO Block Size 00 = 01 = 10 = 11 = 32 byte 16 byte 8 byte 4 byte Note: A change of RFBS will take effect after a receiver command (CMDR.RMC, CMDR.RRES) has been written. SRA Store Receive Address 0= 1= XCRC Receive Address is not stored in the RFIFO Receive Address is stored in the RFIFO Transmit CRC 0= 1= CRC is transmitted CRC is not transmitted RCRC Receive CRC 0= 1= CRC is not stored in the RFIFO CRC is stored in the RFIFO ITF Interframe Time Fill Selects the inter-frame time fill signal which is transmitted between HDLCframes. 0= 1= idle (continuous `1') flags (sequence of patterns: `0111 1110') Note: ITF must be set to `0' for power down mode. In applications with D-channel access handling (collision resolution), the only possible inter-frame time fill is idle (continuous `1'). Otherwise the D-channel on the S/T-bus cannot be accessed. Data Sheet 176 2001-03-30 PEF 81912/81913 Register Description 4.6.9 TIMR TIMR - Timer Register read/write Address: 24H Value after reset: 00H 7 CNT 5 4 VALUE 0 CNT CNT together with VALUE determines the time period T after which a TIN interrupt (ISTA) will be generated in the normal case: CNT=0...6: T = CNT x 2.048 sec + T1 with T1 = (VALUE+1) x 0.064 sec CNT=7: T = T1 = (VALUE+1) x 0.064 sec (generated periodically) The timer can be started by setting the STI-bit in CMDR and will be stopped when a TIN interrupt is generated or the TIMR register is written. Note: If CNT is set to 7, a TIN interrupt is indefinitely generated after every expiration of T = T1. VALUE Determines the time period T1 T1 = (VALUE + 1) x 0.064 sec 4.6.10 SAP1 SAP1 - SAPI1 Register write Address: 25H Value after reset: FCH 7 SAPI1 0 0 MHA SAPI1 SAPI1 value Value of the programmable high address byte. In ISDN LADP protocol (Dchannel) this is the Service Access Point Identifier (SAPI) and for B-channel applications it is the RAH value. Data Sheet 177 2001-03-30 PEF 81912/81913 Register Description MHA Mask High Address 0= 1= The high address of an incoming frame is compared with SAP1, SAP2 and SAPG. The high address of an incoming frame is compared with SAP1 and SAPG. SAP1 can be masked with SAP2. Bit positions of SAP1 are not compared if they are set to `1' in SAP2. 4.6.11 SAP2 SAP2 - SAPI2 Register write Address: 26H Value after reset: FCH 7 SAPI2 0 0 MLA SAPI2 SAPI2 value Value of the programmable high address byte. In ISDN LADP protocol (Dchannel) this is the Service Access Point Identifier (SAPI) and for B-channel applications it is the RAL value. MLA Mask Low Address 0= 1= The TEI address of an incoming frame is compared with TEI1, TEI2 and TEIG. The TEI address of an incoming frame is compared with TEI1 and TEIG. TEI1 can be masked with TEI2. Bit positions of TEI1 are not compared if they are set to `1' in TEI2. Data Sheet 178 2001-03-30 PEF 81912/81913 Register Description 4.6.12 RBCL RBCL - Receive Frame Byte Count Low read Address: 26H Value after reset: 00H 7 RBC7 0 RBC0 RBC7-0 Receive Byte Count Eight least significant bits of the total number of bytes in a received message (see RBCH register). 4.6.13 RBCH RBCH - Receive Frame Byte Count High for D-Channel read Address: 27H Value after reset: 00H. 7 r(0) r(0) r(0) OV RBC11 0 RBC8 OV Overflow 0= 1= Message shorter than (212 - 1) = 4095 bytes. Message longer than (212 - 1) = 4095 bytes. RBC8-11 Receive Byte Count Four most significant bits of the total number of bytes in a received message (see RBCL register). Note: Normally RBCH and RBCL should be read by the microcontroller after a RMEinterrupt, in order to determine the number of bytes to be read from the RFIFO, and the total message length. The contents of the registers are valid only after a RME or RPF interrupt, and remain so until the frame is acknowledged via the RMC bit or RRES. Data Sheet 179 2001-03-30 PEF 81912/81913 Register Description 4.6.14 TEI1 TEI1 - TEI1 Register write Address: 27H Value after reset: FFH 7 TEI1 0 EA1 TEI1 Terminal Endpoint Identifier In all message transfer modes except for transparent modes 0, 1 and extended transparent mode, TEI1 is used by the Q-SMINT(R)IX for address recognition. In the case of a two-byte address field, it contains the value of the first programmable Terminal Endpoint Identifier according to the ISDN LAPD-protocol. EA1 Address Field Extension Bit This bit is set to `1' according to HDLC/LAPD. 4.6.15 TEI2 TEI2 - TEI2 Register write Address: 28H Value after reset: FFH 7 TEI2 0 EA2 TEI2 Terminal Endpoint Identifier In all message transfer modes except in transparent modes 0, 1 and extended transparent mode, TEI2 is used by the Q-SMINT(R)IX for address recognition. In the case of a two-byte address field, it contains the value of the second programmable Terminal Endpoint Identifier according of the ISDN LAPD-protocol. Data Sheet 180 2001-03-30 PEF 81912/81913 Register Description EA2 Address Field Extension Bit This bit is to be set to `1' according to HDLC/LAPD. 4.6.16 RSTA RSTA - Receive Status Register read Address: 28H Value after reset: 0FH 7 VFR RDO CRC RAB SA1 SA0 C/R 0 TA VFR Valid Frame Determines whether a valid frame has been received. A frame is invalid when there is not a multiple of 8 bits between flag and frame end (flag, abort). 0= 1= The frame is invalid The frame is valid RDO Receive Data Overflow 0= 1= No receive data overflow At least one byte of the frame has been lost, because it could not be stored in RFIFO. As opposed the ISTAH.RFO a RDO indicates that the beginning of a frame has been received but not all bytes could be stored as the RFIFO was temporarily full. CRC CRC Check 0= 1= The CRC is incorrect The CRC is correct RAB Receive Message Aborted 0= 1= The receive message was not aborted The receive message was aborted by the remote station, i.e. a sequence of seven 1's was detected before a closing flag. Data Sheet 181 2001-03-30 PEF 81912/81913 Register Description SA1-0 TA SAPI Address Identification TEI Address Identification These bits are only relevant in modes with address comparison. The result of the address comparison is given by SA1-0 and TA, as follows: Address Match with MDS2-0 010 (Non-Auto/8 Mode) 011 (Non-Auto/16 Mode) SA1 x x 0 0 0 0 1 1 0 0 1 1 SA0 x x 0 0 1 1 0 0 0 1 0 1 TA 0 1 0 1 0 1 0 1 x x x 0 1 x 1st Byte TEI2 TEI1 SAP2 SAP2 SAPG SAPG SAP1 SAP1 SAP2 SAPG SAP1 reserved 2nd Byte TEIG TEI2 TEIG TEI1 or TEI2 TEIG TEI1 TEIG TEI1 or TEI2 111 (Transparent Mode 1) 101 (Transparent Mode 2) Note: If SAP1 and SAP2 contain identical values, the combination SAP1,2-TEIG will only be indicated by SAP1,0 = '10' (i.e. the value '00' will not occur in this case). C/R Command/Response The C/R bit contains the C/R bit of the received frame (Bit1 in the SAPI address). Note: The contents of RSTA corresponds to the last received HDLC frame; it is duplicated into RFIFO for every frame (last byte of frame). Data Sheet 182 2001-03-30 PEF 81912/81913 Register Description 4.6.17 TMH TMH -Test Mode Register HDLC read/write Address: 29H Value after reset: 00H 7 r(0) r(0) r(0) r(0) r(0) r(0) r(0) 0 TLP TLP Test Loop 0= 1= inactive The TX path of the HDLC controller is internally connected to its RX path. Data coming from the IOM-2 will not be forwarded to the HDLC controller. Setting of TLP is only valid if IOM-2 is active. Note: The bits7-1 have to be set to "0". 4.6.18 CIR0 CIR0 - Command/Indication Receive 0 read Address: 2EH Value after reset: F3H 7 CODR0 CIC0 CIC1 S/G 0 BAS CODR0 C/I0 Code Receive Value of the received Command/Indication code. A C/I-code is loaded in CODR0 only after being the same in two consecutive IOM-frames and the previous code has been read from CIR0. CIC0 C/I0 Code Change 0= No change in the received Command/Indication code has been recognized Data Sheet 183 2001-03-30 PEF 81912/81913 Register Description 1= A change in the received Command/Indication code has been recognized. This bit is set only when a new code is detected in two consecutive IOM-frames. It is reset by a read of CIR0. CIC1 C/I1 Code Change 0= 1= No change in the received Command/Indication code has been recognized A change in the received Command/Indication code in IOM-channel 1 has been recognized. This bit is set when a new code is detected in one IOM-frame. It is reset by a read of CIR0. S/G Stop/Go Bit Monitoring Indicates the availability of the upstream D-channel; 0= 1= Go Stop BAS Bus Access Status Indicates the state of the TIC-bus: 0= 1= the Q-SMINT(R)IX itself occupies the D- and C/I-channel another device occupies the D- and C/I-channel Note: The CODR0 bits are updated every time a new C/I-code is detected in two consecutive IOM-frames. If several consecutive valid new codes are detected and CIR0 is not read, only the first and the last C/I code are made available in CIR0 at the first and second read of that register. 4.6.19 CIX0 CIX0 - Command/Indication Transmit 0 write Address: 2EH Value after reset: FEH 7 CODX0 TBA2 TBA1 TBA0 0 BAC Data Sheet 184 2001-03-30 PEF 81912/81913 Register Description CODX0 C/I0-Code Transmit Code to be transmitted in the C/I-channel 0. The code is only transmitted if the TIC bus is occupied, otherwise "1s" are transmitted. TBA2-0 TIC Bus Address Defines the individual address for the Q-SMINT(R)IX on the IOM bus. This address is used to access the C/I- and D-channel on the IOM interface. Note: If only one device is liable to transmit in the C/I- and D-channels of the IOM it should always be given the address value `7'. BAC Bus Access Control Only valid if the TIC-bus feature is enabled (MODE:DIM2-0). 0= 1= inactive The Q-SMINT(R)IX will try to access the TIC-bus to occupy the C/Ichannel even if no D-channel frame has to be transmitted. It should be reset when the access has been completed to grant a similar access to other devices transmitting in that IOM-channel. Note: Access is always granted by default to the Q-SMINT(R)IX with TIC-Bus Address (TBA2-0, CIX0 register) `7', which has the lowest priority in a bus configuration. 4.6.20 CIR1 CIR1 - Command/Indication Receive 1 read Address: 2FH Value after reset: FEH 7 CODR1 CICW 0 CI1E CODR1 CICW C/I1-Code Receive C/I-Channel Width Contains the read back value from CIX1 register (see below) 0= 1= 4 bit C/I1 channel width 6 bit C/I1 channel width 185 2001-03-30 Data Sheet PEF 81912/81913 Register Description CI1E C/I1-channel Interrupt Enable Contains the read back value from CIX1 register (see below) 0= 1= Interrupt generation ISTA.CIC of CIR0.CIC1is masked Interrupt generation ISTA.CIC of CIR0.CIC1 is enabled 4.6.21 CIX1 CIX1 - Command/Indication Transmit 1 write Address: 2FH Value after reset: FEH 7 CODX1 CICW 0 CI1E CODX1 C/I1-Code Transmit Bits 5-0 of C/I-channel 1 CICW C/I-Channel Width 0= 1= 4 bit C/I1 channel width 6 bit C/I1 channel width The C/I1 handler always reads and writes 6-bit values but if 4-bit is selected, the higher two bits are ignored for interrupt generation. However, in write direction the full CODX1 code is transmitted, i.e. the host must write the higher two bits to "1". CI1E C/I1-channel Interrupt Enable 0= 1= Interrupt generation ISTA.CIC of CIR0.CIC1is masked Interrupt generation ISTA.CIC of CIR0.CIC1 is enabled 4.7 4.7.1 S_ CONF0 Detailed S-Transceiver Registers S_CONF0 - S-Transceiver Configuration Register 0 read/write Address: 30H Value after reset: 40H Data Sheet 186 2001-03-30 PEF 81912/81913 Register Description 7 DIS_TR BUS EN_ ICV 0 L1SW 0 EXLP 0 0 DIS_TR Disable Transceiver 0= 1= All S-transceiver functions are enabled. All S-transceiver functions are disabled and powered down (analog and digital parts). BUS Point-to-Point / Bus Selection 0= 1= Adaptive Timing (Point-to-Point, extended passive bus). Fixed Timing (Short passive bus), directly derived from transmit clock. EN_ICV Enable Far End Code Violation 0= 1= normal operation. ICV enabled. The receipt of at least one illegal code violation within one multi-frame according to ANSI T1.605 is indicated by the C/I indication `1011' (CVR) in two consecutive IOM frames. L1SW Enable Layer 1 State Machine in Software 0= 1= Layer 1 state machine of the Q-SMINT(R)IX is used. Layer 1 state machine is disabled. The functionality must be realized in software. The commands are written to register S_CMD and the status read in the S_STA. EXLP External Loop In case the analog loopback is activated with C/I = ARL or with the LP_A bit in the S_CMD register the loop is a 0= 1= internal loop next to the line pins external loop which has to be closed between SR1/SR2 and SX1/ SX2 Note: For the external loop the transmitter must be enabled (S_CONF2:DIS_TX = 0). Data Sheet 187 2001-03-30 PEF 81912/81913 Register Description 4.7.2 S_ CONF2 S_CONF2 - S-Transmitter Configuration Register 2 read/write Address: 32H Value after reset: 80H 7 DIS_TX 0 0 0 0 0 0 0 0 DIS_TX Disable Line Driver 0= 1= Transmitter is enabled Transmitter is disabled 4.7.3 S_ STA S_STA - S-Transceiver Status Register read Address: 33H Value after reset: 00H 7 RINF 0 ICV 0 FSYN 0 0 LD Important: This register is used only if the Layer 1 state machine of the device is disabled (S_CONF0:L1SW = 1) and implemented in software! With the layer 1 state machine enabled, the signals from this register are automatically evaluated. RINF Receiver INFO 00 = 01 = 10 = 11 = ICV Received INFO 0 (no signal) Received any signal except INFO 0 or INFO 3 reserved Received INFO 3 Illegal Code Violation 0= 1= No illegal code violation is detected. Illegal code violation (ANSI T1.605) in data stream is detected. Data Sheet 188 2001-03-30 PEF 81912/81913 Register Description FSYN Frame Synchronization State 0= 1= LD The S/T receiver is not synchronized. The S/T receiver has synchronized to the framing bit F. Level Detection 0= 1= No receive signal has been detected on the line. Any receive signal has been detected on the line. 4.7.4 S_ CMD S_CMD - S-Transceiver Command Register read/write Address: 34H Value after reset: 08H 7 XINF DPRIO 1 PD LP_A 0 0 Important: This register - except bit DPRIO - is writable only if the Layer 1 state machine of the device is disabled (S_CONF0.L1SW = 1) and implemented in software! With the device layer 1 state machine enabled, the signals from this register are automatically generated. DPRIO can also be written in intelligent NT mode. XINF Transmit INFO 000 = 001 = 010 = 011 = 100 = 101 = 11x = DPRIO Transmit INFO 0 reserved Transmit INFO 2 Transmit INFO 4 Send continuous pulses at 192 kbit/s alternating or 96 kHz rectangular, respectively (TM2) Send single pulses at 4 kbit/s with alternating polarity corresponding to 2 kHz fundamental mode (TM1) reserved D-Channel Priority 0= Priority class 1 for D channel access on IOM 189 2001-03-30 Data Sheet PEF 81912/81913 Register Description 1= PD Priority class 2 for D channel access on IOM Power Down 0= 1= The transceiver is set to operational mode The transceiver is set to power down mode LP_A Loop Analog The setting of this bit corresponds to the C/I command ARL. 0= 1= Analog loop is open Analog loop is closed internally or externally according to the EXLP bit in the S_CONF0 register 4.7.5 SQRR SQRR - S/Q-Channel Receive Register read Address: 35H Value after reset: 00H 7 MSYN MFEN 0 0 SQR1 SQR2 SQR3 0 SQR4 MSYN Multi-frame Synchronization State 0= 1= The S/T receiver has not synchronized to the received FA and M bits The S/T receiver has synchronized to the received FA and M bits MFEN Multiframe Enable Read-back of the MFEN bit of the SQXR register 0= 1= S/T multiframe is disabled S/T multiframe is enabled SQR1-4 Received S/Q Bits Received Q bits in frames 1, 6, 11 and 16 Data Sheet 190 2001-03-30 PEF 81912/81913 Register Description 4.7.6 SQXR SQXR- S/Q-Channel Transmit Register write Address: 35H Value after reset: 00H 7 0 MFEN 0 0 SQX1 SQX2 SQX3 0 SQX4 MFEN Multiframe Enable Used to enable or disable the multiframe structure. 0= 1= S/T multiframe is disabled S/T multiframe is enabled SQX1-4 Transmitted S/Q Bits Transmitted S bits in frames 1, 6, 11 and 16 4.7.7 ISTAS ISTAS - Interrupt Status Register S-Transceiver read Address: 38H Value after reset: 00H 7 x x x x LD RIC SQC 0 SQW These bits are set if an interrupt status occurs and an interrupt signal is activated if the corresponding mask bit is set to "0". If the mask bit is set to "1" no interrupt is generated, however the interrupt status bit is set in ISTAS. RIC, SQC and SQW are cleared by reading the corresponding source register S_STA, SQRR or writing SQXR, respectively. x LD Reserved Level Detection Data Sheet 191 2001-03-30 PEF 81912/81913 Register Description 0= 1= inactive Any receive signal has been detected on the line. This bit is set to "1" (i.e. an interrupt is generated if not masked) as long as any receive signal is detected on the line. RIC Receiver INFO Change 0= 1= inactive RIC is activated if one of the S_STA bits RINF or ICV has changed. SQC S/Q-Channel Change 0= 1= inactive A change in the received 4-bit Q-channel has been detected. The new code can be read from the SQRx bits of registers SQRR within the next multiframe1). This bit is reset by a read access to the SQRR register. SQW S/Q-Channel Writable 0= 1= inactive The S channel data for the next multiframe is writable. The register for the S bits to be transmitted has to be written within the next multiframe. This bit is reset by writing register SQXR. This timing signal is indicated with the start of every multiframe. Data which is written right after SQW-indication will be transmitted with the start of the following multiframe. Data which is written before SQW-indication is transmitted in the multiframe which is indicated by SQW. SQW and SQC could be generated at the same time. 1) Register SQRR stays valid as long as no code change has been received. 4.7.8 MASKS MASKS - Mask S-Transceiver Interrupt read/write Address: 39H Value after reset: FFH 7 1 1 1 1 LD RIC SQC 0 SQW Data Sheet 192 2001-03-30 PEF 81912/81913 Register Description Bit 3..0 Mask bits 0= 1= The transceiver interrupts LD, RIC, SQC and SQW are enabled The transceiver interrupts LD, RIC, SQC and SQW are masked 4.7.9 S_ MODE S_MODE - S-Transceiver Mode read/write Address: 3AH Value after reset: 02H 7 0 0 0 0 DCH_INH MODE 0 DCH_ INH D-Channel Inhibit 0= 1= inactive The S-transceiver blocks the access to the D-channel on S by inverting the E-bits. MODE Mode Selection 000 = 001 = 010 = 011 = 110 111 100 101 reserved reserved NT (without D-channel handler) LT-S (without D-channel handler) Intelligent NT mode (with NT state machine and with D-channel handler) Intelligent NT mode (with LT-S state machine and with D-channel handler) reserved reserved Data Sheet 193 2001-03-30 PEF 81912/81913 Register Description 4.8 4.8.1 ISTA Interrupt and General Configuration Registers ISTA - Interrupt Status Register read Address: 3CH Value after reset: 00H 7 U ST CIC TIN WOV S MOS 0 HDLC U U-Transceiver Interrupt 0= 1= inactive An interrupt was generated by the U-transceiver. Read the ISTAU register. ST Synchronous Transfer 0= 1= inactive This interrupt enables the microcontroller to lock on to the IOM(R)-2 timing, for synchronous transfers. CIC C/I Channel Change 0= 1= inactive A change in C/I0 channel or C/I1 channel has been recognized. The actual value can be read from CIR0 or CIR1. TIN Timer Interrupt 0= 1= inactive The internal timer and repeat counter has expired (see TIMR register). WOV Watchdog Timer Overflow 0= inactive Data Sheet 194 2001-03-30 PEF 81912/81913 Register Description 1= Signals the expiration of the watchdog timer, which means that the microcontroller has failed to set the watchdog timer control bits WTC1 and WTC2 (MODE1 register) in the correct manner. A reset out pulse on pin RSTO has been generated by the Q-SMINT(R)IX. S S-Transceiver Interrupt 0= 1= inactive An interrupt was generated by the S-transceiver. Read the ISTAS register. MOS MONITOR Status 0= 1= inactive A change in the MONITOR Status Register (MOSR) has occurred. HDLC HDLC Interrupt 0= 1= inactive An interrupt originated in the HDLC interrupt sources has been recognized. Note: A read of the ISTA register clears only the TIN and WOV interrupts. The other interrupts are cleared by reading the corresponding status register. 4.8.2 MASK MASK - Mask Register write Address: 3CH Value after reset: FFH 7 U ST CIC TIN WOV S MOS 0 HDLC Bit 7..0 Mask bits 0= 1= Interrupt is not masked Interrupt is masked Data Sheet 195 2001-03-30 PEF 81912/81913 Register Description Each interrupt source in the ISTA register can be selectively masked by setting the corresponding bit in MASK to `1'. Masked interrupt status bits are not indicated when ISTA is read. Instead, they remain internally stored and pending, until the mask bit is reset to `0'. Note: In the event of a C/I channel change, CIC is set in ISTA even if the corresponding mask bit in MASK is active, but no interrupt is generated. 4.8.3 MODE1 MODE1 - Mode1 Register read/write Address: 3DH Value after reset: 04H 7 MCLK CDS WTC1 WTC2 CFS RSS2 0 RSS1 MCLK Master Clock Frequency The Master Clock Frequency bits control the microcontroller clock output depending on MODE1.CDS = '0' or '1' (Table Table 2.1.3). MODE1.CDS = '0' 00 = 01 = 10 = 11 = 3.84 MHz 0.96 MHz 7.68 MHz disabled MODE1.CDS = '1' 7.68 MHz 1.92 MHz 15.36 MHz disabled CDS Clock Divider Selection 0= 1= The 15.36 MHz oscillator clock divided by two is input to the MCLK prescaler The 15.36 MHz oscillator clock is input to the MCLK prescaler. WTC1, 2 Watchdog Timer Control 1, 2 After the watchdog timer mode has been selected (RSS = `11') the watchdog timer is started. During every time period of 128 ms the microcontroller has to program the WTC1 and WTC2 bit in the following sequence (Chapter 2.2): 10 first step Data Sheet 196 2001-03-30 PEF 81912/81913 Register Description 01 second step to reset and restart the watchdog timer. If not, the timer expires and a WOV-interrupt (ISTA Register) together with a reset out pulse on pin RSTO is generated. The watchdog timer runs only when the internal IOM(R)-2 clocks are active, i.e. the watchdog timer is dead when bit CFS = 1 and the U and Stransceivers are in state power down. CFS Configuration Select 0= The IOM(R)-2 interface clock and frame signals are always active, "Deactivated State" of the U-transceiver and the S-transceiver included. The IOM(R)-2 interface clocks and frame signals are inactive in the "Deactivated State" of the U-transceiver and the S-transceiver. 1= RSS2, RSS1 Reset Source Selection 2,1 The Q-SMINT(R)IX reset sources can be selected according to the table below. C/I Code Change 00 = 01 = 10 = 11 = x --Watchdog Timer --x POR/UVD and RST x x x RSTO disabled (high impedance) 4.8.4 MODE2 MODE2 - Mode2 Register read/write Address: 3EH Value after reset: 00H 7 LED2 LED1 LEDC 0 0 0 AMOD 0 PPSDX LED2,1 LED Control on pin ACT 00 = High 197 2001-03-30 Data Sheet PEF 81912/81913 Register Description 01 = 10 = 11 = LEDC flashing at 8 Hz flashing at 1 Hz Low LED Control Enable 0= 1= LED is controlled by the state machines as defined in Table 4. LED is controlled via bits LED2,1. AMOD Address Mode Selects between direct and indirect register access of the parallel microcontroller interface. 0= 1= Indirect address mode is selected. The address line A0 is used to select between address (A0 = `0') and data (A0 = `1') register Direct address mode is selected. The address is applied to the address bus (A0-A6) PPSDX Push/Pull Output for SDX 0= 1= The SDX pin has open drain characteristic The SDX pin has push/pull characteristic 4.8.5 ID ID - Identification Register read Address: 3FH Value after reset: 01H 7 0 0 DESIGN 0 Data Sheet 198 2001-03-30 PEF 81912/81913 Register Description DESIGN Design Number The design number (DESIGN) allows to identify different hardware designs1) of the Q-SMINT(R)IX by software. 000000: Version 1.1 000001: Version 1.2 000001: Version 1.3 1) Distinction of different firmware versions is also possible by reading register (7D)H in the address space of the U-transceiver (see Chapter 4.11.19). 4.8.6 SRES SRES - Software Reset Register write Address: 3FH Value after reset: 00H 7 0 0 RES_ CI/TIC 0 RES_ HDLC 0 RES_S 0 RES_U RES_xx Reset_xx 0= 1= Deactivates the reset of the functional block xx Activates the reset of the functional block xx. The reset state is activated as long as the bit is set to `1' 4.9 4.9.1 Detailed IOM(R)-2 Handler Registers CDAxy - Controller Data Access Register xy These registers are used for microcontroller access to the IOM(R)-2 timeslots as well as for timeslot manipulations. (e.g. loops, shifts, ... see also "Controller Data Access (CDA)" on Page 31). Data Sheet 199 2001-03-30 PEF 81912/81913 Register Description CDAxy 7 Controller Data Access Register Data register CDAxy which can be accessed by the controller. Register CDA10 CDA11 CDA20 CDA21 Value after Reset FFH FFH FFH FFH Register Address 40H 41H 42H 43H read/write Address: 40-43H 0 4.9.2 XXX_TSDPxy - Time Slot and Data Port Selection for CHxy read/write Address: 44-4DH 0 0 0 0 TSS XXX_TSDPxy 7 DPS Register CDA_TSDP10 CDA_TSDP11 CDA_TSDP20 CDA_TSDP21 S_TSDP_B1 S_TSDP_B2 Value after Reset 00H (= output on B1-DD) 01H (= output on B2-DD) 80H (= output on B1-DU) 81H (= output on B2-DU) reserved 84H (= output on TS4-DU) 85H (= output on TS5-DU) Register Address 44H 45H 46H 47H 48-4BH 4CH 4DH This register determines the time slots and the data ports on the IOM(R)-2 Interface for the data channels xy of the functional units XXX (Controller Data Access (CDA) and Stransceiver (S)). Note: The U-transceiver is always in IOM-2 channel 0. Data Sheet 200 2001-03-30 PEF 81912/81913 Register Description DPS Data Port Selection 0= 1= The data channel xy of the functional unit XXX is output on DD. The data channel xy of the functional unit XXX is input from DU. The data channel xy of the functional unit XXX is output on DU. The data channel xy of the functional unit XXX is input from DD. Note: For the CDA (controller data access) data the input is determined by the CDAx_CR.SWAP bit. If SWAP = `0' the input for the CDAxy data is vice versa to the output setting for CDAxy. If the SWAP = `1' the input from CDAx0 is vice versa to the output setting of CDAx1 and the input from CDAx1 is vice versa to the output setting of CDAx0. TSS Timeslot Selection Selects one of the 12 timeslots from 0...11 on the IOM(R)-2 interface for the data channels. 4.9.3 CDAx_CR 7 0 CDAx_CR - Control Register Controller Data Access CH1x read/write Address: 4E-4FH 0 0 EN_TBM EN_I1 EN_I0 EN_O1 EN_O0 SWAP Register CDA1_CR CDA2_CR Value after Reset 00H 00H Register Address 4EH 4FH EN_TBM Enable TIC Bus Monitoring 0= 1= The TIC bus monitoring is disabled The TIC bus monitoring with the CDAx0 register is enabled. The TSDPx0 register must be set to 08H for monitoring from DU, or 88H for monitoring from DD. EN_I1, EN_I0 Data Sheet Enable Input CDAx1, CDAx0 201 2001-03-30 PEF 81912/81913 Register Description 0= 1= EN_O1, EN_O0 The input of the CDAx1, CDAx0 register is disabled The input of the CDAx1, CDAx0 register is enabled Enable Output CDAx1, CDAx0 0= 1= The output of the CDAx1, CDAx0 register is disabled The output of the CDAx1, CDAx0 register is enabled SWAP Swap Inputs 0= The time slot and data port for the input of the CDAxy register is defined by its own TSDPxy register. The data port for the CDAxy input is vice versa to the output setting for CDAxy. The input (time slot and data port) of the CDAx0 is defined by the TSDP register of CDAx1 and the input of CDAx1 is defined by the TSDP register of CDAx0. The data port for the CDAx0 input is vice versa to the output setting for CDAx1. The data port for the CDAx1 input is vice versa to the output setting for CDAx0. The input definition for time slot and data port CDAx0 are thus swapped to CDAx1 and for CDAx1 to CDAx0. The outputs are not affected by the SWAP bit. 1= 4.9.4 S_CR S_CR - Control Register S-Transceiver Data read/write Address: 51H Value after reset: FFH 7 1 CI_CS EN_D EN_B2R EN_B1R EN_B2X EN_B1X 0 D_CS CI_CS C/I Channel Selection This bit is used to select the IOM channel to which the S-transceiver C/Ichannel is related to. 0= 1= C/I-channel in IOM-channel 0 C/I-channel in IOM-channel 1 Data Sheet 202 2001-03-30 PEF 81912/81913 Register Description EN_D Enable Transceiver D-Channel Data 0= 1= EN_B2R The corresponding data path to the transceiver is disabled The corresponding data path to the transceiver is enabled. Enable Transceiver B2 Receive Data (transmitter receives from IOM) 0= 1= The corresponding data path to the transceiver is disabled The corresponding data path to the transceiver is enabled. EN_B1R Enable Transceiver B1 Receive Data (transmitter receives from IOM) 0= 1= The corresponding data path to the transceiver is disabled The corresponding data path to the transceiver is enabled. EN_B2X Enable Transceiver B2 Transmit Data (transmitter transmits to IOM) 0= 1= The corresponding data path to the transceiver is disabled The corresponding data path to the transceiver is enabled. EN_B1X Enable Transceiver B1 Transmit Data (transmitter transmits to IOM) 0= 1= The corresponding data path to the transceiver is disabled The corresponding data path to the transceiver is enabled. These bits are used to individually enable/disable the D-channel and the receive/transmit paths for the B-channels for the S-transceiver. D_CS D Channel Selection This bit is used to select the IOM channel to which the S-transceiver Dchannel is related to. 0= 1= D-channel in IOM-channel 0 D-channel in IOM-channel 1 Data Sheet 203 2001-03-30 PEF 81912/81913 Register Description 4.9.5 HCI_CR HCI_CR - Control Register for HDLC and CI1 Data read/write Address: 52H Value after reset: 04H 7 DPS_CI1 EN_CI1 EN_D EN_B2H EN_B1H DPS_H HCS 0 DPS_CI1 Data Port Selection CI1 Handler 0= 1= EN_CI1 The CI1 data is output on DD and input from DU The CI1 data is output on DU and input from DD Enable CI1 Handler 0= 1= CI1 data access is disabled CI1 data access is enabled Note: The timeslot for the C/I1 handler cannot be programmed but is fixed to IOM channel 1. EN_D Enable D-timeslot for HDLC controller 0= 1= EN_B2H The HDLC controller does not access timeslot data D The HDLC controller does access timeslot data D Enable B2-timeslot for HDLC controller 0= 1= The HDLC controller does not access timeslot data B2 The HDLC controller does access timeslot data B2 EN_B1H Enable B1-timeslot for HDLC controller 0= 1= The HDLC controller does not access timeslot data B1 respectively The HDLC controller does access timeslot data B1 The bits EN_D, EN_B2H and EN_B1H are used to select the timeslot length for the Dchannel HDLC controller access as it is capable to access not only the D-channel timeslot. The host can individually enable two 8-bit timeslots B1- and B2-channel, i.e. the first and second octett, (EN_B1H, EN_B2H) and one 2-bit timeslot D-channel (EN_D) on IOM-2. The position is selected via HCS. Data Sheet 204 2001-03-30 PEF 81912/81913 Register Description DPS_H Data Port Selection HDLC 0= 1= HCS Transmit on DD, receive on DU Transmit on DU, receive on DD HDLC Channel Selection These two bits determine the IOM(R)-2 channel of the HDLC controller. The HDLC controller will read and write HDLC data into the selected B1, B2 and D channel timeslots of the selected IOM(R)-2 channel. 00 = 01 = 10 = 11 = The HDLC data is read and output on IOM-channel 0 The HDLC data is read and output on IOM-channel 1 The HDLC data is read and output on IOM-channel 21) Not defined 1) If the TIC-bus is enabled, then an HDLC access in IOM-channel 2 is possible only to the B channels. 4.9.6 MON_CR MON_CR - Control Register Monitor Data read/write Address: 53H Value after reset: 40H 7 DPS EN_MON 0 0 0 0 MCS 0 DPS Data Port Selection 0= 1= The Monitor data is output on DD and input from DU The Monitor data is output on DU and input from DD EN_MON Enable Output 0= 1= MCS The Monitor data input and output is disabled The Monitor data input and output is enabled MONITOR Channel Selection 00 = The MONITOR data is output on MON0 01 = The MONITOR data is output on MON1 Data Sheet 205 2001-03-30 PEF 81912/81913 Register Description 10 = The MONITOR data is output on MON2 11 = Not defined 4.9.7 SDS1_CR SDS1_CR - Control Register Serial Data Strobe 1 read/write Address: 54H Value after reset: 00H 7 ENS_ TSS ENS_ TSS+1 ENS_ TSS+3 0 TSS 0 This register is used to select position and length of the strobe signal 1. The length can be any combination of two 8-bit timeslot (ENS_TSS, ENS_TSS+1) and one 2-bit timeslot (ENS_TSS+3). ENS_ TSS Enable Serial Data Strobe of timeslot TSS 0= 1= ENS_ TSS+1 The serial data strobe signal SDS1 is inactive during TSS The serial data strobe signal SDS1 is active during TSS Enable Serial Data Strobe of timeslot TSS+1 0= 1= The serial data strobe signal SDS1 is inactive during TSS+1 The serial data strobe signal SDS1 is active during TSS+1 ENS_ TSS+3 Enable Serial Data Strobe of timeslot TSS+3 (D-Channel) 0= 1= The serial data strobe signal SDS1 is inactive during the D-channel (bit7, 6) of TSS+3 The serial data strobe signal SDS1 is active during the D-channel (bit7, 6) of TSS+3 TSS Timeslot Selection Selects one of 12 timeslots on the IOM(R)-2 interface (with respect to FSC) during which SDS1 is active high. The data strobe signal allows standard data devices to access a programmable channel. Data Sheet 206 2001-03-30 PEF 81912/81913 Register Description 4.9.8 SDS2_CR SDS2_CR - Control Register Serial Data Strobe 2 read/write Address: 55H Value after reset: 00H 7 ENS_ TSS ENS_ TSS+1 ENS_ TSS+3 0 TSS 0 This register is used to select position and length of the strobe signal 2. The length can be any combination of two 8-bit timeslot (ENS_TSS, ENS_TSS+1) and one 2-bit timeslot (ENS_TSS+3). ENS_ TSS Enable Serial Data Strobe of timeslot TSS 0= 1= ENS_ TSS+1 The serial data strobe signal SDS2 is inactive during TSS The serial data strobe signal SDS2 is active during TSS Enable Serial Data Strobe of timeslot TSS+1 0= 1= The serial data strobe signal SDS2 is inactive during TSS+1 The serial data strobe signal SDS2 is active during TSS+1 ENS_ TSS+3 Enable Serial Data Strobe of timeslot TSS+3 (D-Channel) 0= 1= The serial data strobe signal SDS2 is inactive during the D-channel (bit7, 6) of TSS+3 The serial data strobe signal SDS2 is active during the D-channel (bit7, 6) of TSS+3 TSS Timeslot Selection Selects one of 12 timeslots on the IOM(R)-2 interface (with respect to FSC) during which SDS2 is active high. The data strobe signal allows standard data devices to access a programmable channel. Data Sheet 207 2001-03-30 PEF 81912/81913 Register Description 4.9.9 IOM_CR IOM_CR - Control Register IOM Data read/write Address: 56H Value after reset: 08H 7 SPU 0 0 TIC_DIS EN_BCL 0 0 DIS_OD DIS_IOM SPU Software Power UP 0= 1= The DU line is normally used for transmitting data. Setting this bit to `1' will pull the DU line to low. This will enforce the Q-SMINT(R)IX and other connected layer 1 devices to deliver IOMclocking. TIC_DIS TIC Bus Disable 0= 1= The last octet of the last IOM time slot (TS 11) is used as TIC bus. The TIC bus is disabled. The last octet of the last IOM time slot (TS 11) can be used like any other time slot. This means that the timeslots TIC, A/B, S/G and BAC are not available any more. EN_BCL Enable Bit Clock BCL 0= 1= The BCL clock is disabled (output is high impedant) The BCL clock is enabled DIS_OD Disable Open Drain 0= 1= IOM outputs are open drain driver IOM outputs are push pull driver DIS_IOM Disable IOM DIS_IOM should be set to `1' if external devices connected to the IOM interface should be "disconnected" e.g. for power saving purposes. However, the Q-SMINT(R)IX internal operation is independent of the DIS_IOM bit. Data Sheet 208 2001-03-30 PEF 81912/81913 Register Description 0= 1= The IOM interface is enabled The IOM interface is disabled (FSC, DCL, clock outputs have high impedance; DU, DD data line inputs are switched off and outputs are high impedant) 4.9.10 MCDA MCDA - Monitoring CDA Bits read Address: 57H Value after reset: FFH 7 MCDA21 Bit7 Bit6 MCDA20 Bit7 Bit6 MCDA11 Bit7 Bit6 0 MCDA10 Bit7 Bit6 MCDAxy Monitoring CDAxy Bits Bit 7 and Bit 6 of the CDAxy registers are mapped into the MCDA register. This can be used for monitoring the D-channel bits on DU and DD and the "Echo bits" on the TIC bus with the same register. 4.9.11 STI STI - Synchronous Transfer Interrupt read Address: 58H Value after reset: 00H 7 STOV21 STOV20 STOV11 STOV10 STI21 STI20 STI11 0 STI10 For all interrupts in the STI register the following logical states are applied 0= 1= STOVxy Interrupt has not occurred Interrupt has occurred Synchronous Transfer Overflow Interrupt Data Sheet 209 2001-03-30 PEF 81912/81913 Register Description Enabled STOV interrupts for a certain STIxy interrupt are generated when the STIxy has not been acknowledged in time via the ACKxy bit in the ASTI register. This must be one (for DPS = `0') or zero (for DPS = `1') BCL clock cycles before the time slot which is selected for the STOV. STIxy Synchronous Transfer Interrupt Depending on the DPS bit in the corresponding TSDPxy register the Synchronous Transfer Interrupt STIxy is generated two (for DPS = `0') or one (for DPS = `1') BCL clock cycles after the selected time slot (TSDPxy.TSS). Note: ST0Vxy and ACKxy are useful for synchronizing microcontroller accesses and receive/transmit operations. One BCL clock is equivalent to two DCL clocks. 4.9.12 ASTI ASTI - Acknowledge Synchronous Transfer Interrupt write Address: 58H Value after reset: 00H 7 0 0 0 0 ACK21 ACK20 ACK11 0 ACK10 ACKxy Acknowledge Synchronous Transfer Interrupt After a STIxy interrupt the microcontroller has to acknowledge the interrupt by setting the corresponding ACKxy bit. 0= 1= No activity is initiated Sets the acknowledge bit ACKxy for a STIxy interrupt 4.9.13 MSTI MSTI - Mask Synchronous Transfer Interrupt read/write Address: 59H Value after reset: FFH 7 STOV21 STOV20 STOV11 STOV10 Data Sheet 210 0 STI21 STI20 STI11 STI10 2001-03-30 PEF 81912/81913 Register Description For the MSTI register the following logical states are applied: 0= 1= STOVxy Interrupt is not masked Interrupt is masked Mask Synchronous Transfer Overflow xy Mask bits for the corresponding STOVxy interrupt bits. STIxy Synchronous Transfer Interrupt xy Mask bits for the corresponding STIxy interrupt bits. 4.10 4.10.1 MOR Detailed MONITOR Handler Registers MOR - MONITOR Receive Channel read Address: 5CH Value after reset: FFH 7 0 Contains the MONITOR data received in the IOM(R)-2 MONITOR channel according to the MONITOR channel protocol. The MONITOR channel (0,1,2) can be selected by setting the monitor channel select bit MON_CR.MCS. 4.10.2 MOX MOX - MONITOR Transmit Channel write Address: 5CH Value after reset: FFH 7 0 Contains the MONITOR data to be transmitted in IOM(R)-2 MONITOR channel according to the MONITOR channel protocol. The MONITOR channel (0,1,2) can be selected by setting the monitor channel select bit MON_CR.MCS Data Sheet 211 2001-03-30 PEF 81912/81913 Register Description 4.10.3 MOSR MOSR - MONITOR Interrupt Status Register read Address: 5DH Value after reset: 00H 7 MDR MER MDA MAB 0 0 0 0 0 MDR MONITOR channel Data Received 0= 1= inactive MONITOR channel Data Received MER MONITOR channel End of Reception 0= 1= inactive MONITOR channel End of Reception MDA MONITOR channel Data Acknowledged The remote end has acknowledged the MONITOR byte being transmitted. 0= 1= inactive MONITOR channel Data Acknowledged MAB MONITOR channel Data Abort 0= 1= inactive MONITOR channel Data Abort 4.10.4 MOCR MOCR - MONITOR Control Register read/write Address: 5EH Value after reset: 00H 7 MRE MRC MIE MXC 0 0 0 0 0 Data Sheet 212 2001-03-30 PEF 81912/81913 Register Description MRE MONITOR Receive Interrupt Enable 0= 1= MRC MONITOR interrupt status MDR generation is masked. MONITOR interrupt status MDR generation is enabled. MR Bit Control Determines the value of the MR bit: 0= 1= MR is always `1'. In addition, the MDR interrupt is blocked, except for the first byte of a packet (if MRE = 1). MR is internally controlled by the Q-SMINT(R)IX according to MONITOR channel protocol. In addition, the MDR interrupt is enabled for all received bytes according to the MONITOR channel protocol (if MRE = 1). MIE MONITOR Interrupt Enable 0= 1= MONITOR interrupt status MER, MDA, MAB generation is masked MONITOR interrupt status MER, MDA, MAB generation is enabled MXC MX Bit Control Determines the value of the MX bit: 0= 1= The MX bit is always `1'. The MX bit is internally controlled by the Q-SMINT(R)IX according to MONITOR channel protocol. 4.10.5 MSTA MSTA - MONITOR Status Register read Address: 5FH Value after reset: 00H 7 0 0 0 0 0 MAC 0 0 TOUT MAC MONITOR Transmit Channel Active 0= No data transmission in the MONITOR channel Data Sheet 213 2001-03-30 PEF 81912/81913 Register Description 1= TOUT The data transmission in the MONITOR channel is in progress. Time-Out Read-back value of the TOUT bit 0= 1= The monitor time-out function is disabled The monitor time-out function is enabled 4.10.6 MCONF MCONF - MONITOR Configuration Register write Address: 5FH Value after reset: 00H 7 0 0 0 0 0 0 0 0 TOUT TOUT Time-Out 0= 1= The monitor time-out function is disabled The monitor time-out function is enabled 4.11 4.11.1 Detailed U-Transceiver Registers OPMODE - Operation Mode Register The Operation Mode register determines the operating mode of the U-transceiver. OPMODE Reset Value: 7 0 14H 6 UCI 5 FEBE 4 MLT 3 0 2 CI_SEL 1 0 0 0 read*)/write Address: 60H UCI Enable/Disable C Control of C/I Codes Data Sheet 214 2001-03-30 PEF 81912/81913 Register Description 0= 1= C control disabled - C/I codes are exchanged via IOM(R)-2 Read access to register UCIR by the P is still possible C control enabled - C/I codes are exchanged via UCIR and UCIW registers In this case, the according C/I-channel on IOM(R)-2 is idle `1111` FEBE Enable/Disable External Write Access to FEBE Bit in Register M56W 0= 1= external access to FEBE bit disabled - FEBE bit is controlled by internal FEBE counter external access to FEBE bit enabled - FEBE bit is controlled by external microprocessor MLT Enable/Disable Metallic Loop Termination Function MLT status is reflected in bit MS2 and MS1 in register M56R 0= 1= MLT disabled MLT enabled CI_SEL C/I Code Output Selection by CI_SEL the user can switch: - between the standard C/I indications of the NT state machine as implemented in today's IEC-Q versions or - newly defined C/I code indications which facilitates control and debugging 0= 1= Standard NT state machine compliant to NT state machine of today's IEC-Q V4.3-V5.3 Simplified NT state machine output of newly defined C/I code indications for enhanced activation/deactivation control and debugging facilities 4.11.2 MFILT - M Bit Filter Options The M Bit Filter register defines the validation algorithm received Maintenance channel bits (EOC, M4, M56) of the U-interface have to undergo before they are approved and passed on to the C. MFILT Reset Value: 7 14H 6 5 4 3 2 1 0 read*)/write Address: 61H Data Sheet 215 2001-03-30 PEF 81912/81913 Register Description M56 FILTER M4 FILTER EOC FILTER M56 FILTER controls the validation mode of the spare bits (M51, M52, M61) on a per bit base (see Chapter 2.4.4.3). X0 = X1 = Apply same filter to M5 and M6 bit data as programmed for M4 bit data. On Change M4 Filter 3-bit field which controls the validation mode of the M4 bits on a per bit base (see Chapter 2.4.4.1). x00 = x01 = x10 = x11 = 0xx = 1xx = On Change TLL coverage of M4 bit data CRC coverage of M4 bit data CRC and TLL coverage of M4 bit data M4 bits towards state machine are covered by TLL. M4 bits towards state machine are checked by the same validation algorithm as programmed for the reporting to the system interface (see Chapter 2.4.4.2). EOC FILTER 3-bit field which controls the processing of EOC messages and its verification algorithm (see Chapter 2.4.3.3). 100 = 001 = 010 = 011 = EOC automatic mode EOC transparent mode without any filtering EOC transparent mode with `on change' filtering EOC transparent mode with Triple-Last-Look (TLL) Filtering 4.11.3 EOCR - EOC Read Register The EOC Read register contains the last verified EOC message (M1-M3 bits) according to the verification criterion selected in MFILT.EOC FILTER. EOCR Reset Value: 0FFFH 15 14 13 12 11 10 9 8 read Address: 63H Data Sheet 216 2001-03-30 PEF 81912/81913 Register Description 0 7 i1 0 6 i2 0 5 i3 0 4 i4 a1 3 i5 a2 2 i6 a3 1 i7 d/m 0 i8 EOC a1 .. a3 d/m i1 .. i8 Embedded Operations Channel (see Chapter 2.4.3) address field data/ message indicator information field, 4.11.4 EOCW - EOC Write Register Via the EOC Write register, the EOC message (M1-M3 bits) of the next available U superframe can be sent and it will be repeated until a new value is written to EOCW, or the line is deactivated. Access to the EOCW register is reasonably only if the EOC channel is operated in `Transparent mode', otherwise conflicts with the internal EOC processor may occur. EOCW Reset Value: 0100H 15 0 7 i1 14 0 6 i2 13 0 5 i3 12 0 4 i4 11 a1 3 i5 10 a2 2 i6 9 a3 1 i7 8 d/m 0 i8 write Address: 65H a1 .. a3 d/m address field data/ message indicator Data Sheet 217 2001-03-30 PEF 81912/81913 Register Description i1 .. i8 information field (8 codes are reserved by ANSI/ETSI for diagnostic and loopback functions) 4.11.5 M4RMASK - M4 Read Mask Register Via the M4 Read Mask register, the user can selectively control which M4 bit changes are reported via interrupt requests. M4RMASK Reset Value: 7 00H 6 5 4 3 2 1 0 read*)/write Address: 67H M4 Read Mask Bits Bit 0..7 0= 1= M4 bit change indication by interrupt active M4 bit change indication by interrupt masked 4.11.6 M4WMASK - M4 Write Mask Register Access to the M4 Write Mask register (M4W) is controlled by the M4WMASK register. By means of the M4WMASK register the user can control on a per bit base which M4 bits are controlled by the user and which are controlled by the state machine. M4WMASK Reset Value: 7 A8H 6 5 4 3 2 1 0 read*)/write Address: 68H M4 Write Mask Bits Bit 0..7 0= 1= Bit 6 M4 bit is controlled by state machine/ external pins (PS1,2) M4 bit is controlled by C Partial Activation Control External/Automatic, function corresponds to the MON-8 commands PACE and PACA 218 2001-03-30 Data Sheet PEF 81912/81913 Register Description 0= 1= SAI bit is controlled and UOA bit is evaluated by state machine SAI bit is controlled via the C, UOA=1 is reported to the state machine 4.11.7 M4R - M4 Read The Read M4 bit register contains the last received and verified M4 bit data. M4R Reset Value: 7 AIB BEH 6 UOA 5 M46 4 M45 3 M44 2 SCO 1 DEA 0 ACT read Address: 69H AIB Interruption (according to ANSI) 0= 1= indicates interruption inactive UOA U Activation Only 0= 1= indicates that only U is activated inactive SCO Start-on-Command Only Bit indicates whether the DLC network will deactivate the loop between calls (defined in Bellcore TR-NWT000397) 0= Start-on-Command-Only mode active, in LULT mode the U-transceiver shall initiate the start-up procedure only upon command from the network (`AR' primitive) normal mode, if the U-transceiver is operated within a DCL configuration as LULT it shall start operation as soon as power is applied 1= DEA Deactivation Bit 0= 1= LT informs NT that it will turn off inactive Data Sheet 219 2001-03-30 PEF 81912/81913 Register Description ACT Activation Bit 0= 1= layer 2 not established signals layer 2 ready for communication 4.11.8 M4W - M4 Write Register Via the M4 bit Write register the M4 bits of the next available U-superframe and subsequent ones can be controlled. The value is latched and transmitted until a new value is set. M4W Reset Value: 7 NIB BEH 6 SAI 5 M46 4 CSO 3 NTM 2 PS2 1 PS1 0 ACT write Address: 6AH NIB Network Indication Bit 0= 1= no function (reserved for network use) no function (reserved for network use) SAI S Activity Indicator 0= 1= S-interface is deactivated S-interface is activated CSO Cold Start Only 0= 1= NT is capable to perform warm starts NT activation with cold start only NTM NT Test Mode 0= 1= NT busy in test mode inactive PS2 Power Status Secondary Source 0= secondary power supply failed Data Sheet 220 2001-03-30 PEF 81912/81913 Register Description 1= PS1 secondary power supply ok Power Status Primary Source 0= 1= primary power supply failed primary power supply ok ACT Activation Bit 0= 1= layer 2 not established signals layer 2 ready for communication 4.11.9 M56R - M56 Read Register Bits 1 to 3 of the M5, M6 bit Read register contain the last verified M5, M6 bit information. Bits 5 and 6 reflect the current MLT state (MS2,1). The FEBE/NEBE error indication bits are accommodated at bit positions 0 and 4. They signal that a FEBE and/or NEBE error have/has occurred. M56R Reset Value: 7 0 1FH 6 MS2 5 MS1 4 NEBE 3 M61 2 M52 1 M51 0 FEBE read Address: 6BH MS1,2 MLT Status 00 = 01 = 10 = 11 = Normal Mode Insertion Loss Quiet Mode Reserved NEBE Near-End Block Error 0= 1= Near-End Block Error has occurred no Near-End Block Error has occurred M61, Received Spare Bits of last U superframe (M51, M52 and M61 have no M52, M51 effect on the Q-SMINT(R)IX ). Data Sheet 221 2001-03-30 PEF 81912/81913 Register Description FEBE Far-End Block Error 0= 1= Far-End Block Error has occurred no Far-End Block Error has occurred 4.11.10 M56W - M56 Write Register Via the M56 bit Write register, the M5 and M6 bits of the next available superframe can be set. The value is latched and transmitted as long as a new value is set or the function is disabled. The FEBE bit can only be set and controlled externally if OPMODE.FEBE is set to `1'. M56W Reset Value: 7 1 FFH 6 1 5 1 4 1 3 M61 2 M52 1 M51 0 FEBE write Address: 6CH M61, Transmitted Spare Bits to next U superframe (M51, M52 and M61 have no M52, M51 effect on the Q-SMINT(R)IX. FEBE Far-End Block Error 0= 1= Far-End Block Error has occurred no Far-End Block Error has occurred 4.11.11 UCIR - C/I Code Read Register Via the U-transceiver C/I code Read register a microcontroller can access the C/I code that is output from the state machine. UCIR Reset Value: 7 0 00H 6 0 5 0 4 0 3 2 1 0 read Address: 6DH C/I code output Data Sheet 222 2001-03-30 PEF 81912/81913 Register Description 4.11.12 UCIW - C/I Code Write Register The U-transceiver C/I code Write register allows a microcontroller to control the state of the U-transceiver. To enable this function bit UCI in register OPMODE must be set to `1' before. UCIW Reset Value: 7 0 01H 6 0 5 0 4 0 3 2 1 0 write Address: 6EH C/I code input 4.11.13 TEST - Test Register The Test register sets the U-transceiver in the desired test mode. TEST Reset Value: 7 0 00H 6 0 5 0 4 0 3 CCRC 2 +-1 tones 1 0 0 40kHz read*)/write Address: 6FH CCRC Send Corrupt CRC 0= 1= inactive send corrupt (inverted) CRCs +-1 tones Send +/-1 Pulses Instead of +/-3 0= 1= 40kHz issues +/-3 pulses during 40 kHz tone generation or in SSP mode issues +/-1 pulses 40 kHz Test Signal 0= 1= issues single pulses in state 'Test' issues a 40 kHz test signal in state 'Test' Data Sheet 223 2001-03-30 PEF 81912/81913 Register Description 4.11.14 LOOP - Loop Back Register The Loop register controls the digital loopbacks of the U-transceiver. The analog loopback (No. 3) is closed by C/I= `ARL'. Note: If the EOC automatic mode is selected (MFILT.EOC Filter = '100'), then register LOOP is accessed by the internal EOC processor: EOC-command 'LB1' ('LB2') sets LOOP.U/IOM and LOOP.LB1 (LOOP.LB2) EOC-command 'RTN' resets LOOP.LB1, LOOP.LB2 and LOOP.LBBD LOOP Reset Value: 7 0 08H 6 DLB 5 TRANS 4 U/IOM 3 1 2 LBBD 1 LB2 0 LB1 read*)/write Address: 70H DLB Close Framer/Deframer Loopback - the loopback is closed at the analog/digital interface - prerequisite is that LB1, LB2, LBBD and U/IOM(R) are set to `0' - only user data is looped and no maintenance data is looped back1) 0= 1= Framer/Deframer loopback open Framer/Deframer loopback closed TRANS Transparent/ Non-Transparent Loopback - in transparent mode user data is both passed on and looped back, whereas in non-transparent mode data is not forwarded but substituted by '1's (idle code) and just looped back2) - if LBBD, LB2, LB1 is closed towards the IOM(R) interface and bit TRANS is set to '0' then the state machine has to be put into state 'Transparent' first (e.g. by C/I = DT) before data is output on the U-interface - bit TRANS has no effect on DLB and the analog loopback (ARL operates always in transparent mode) 0= 1= sets transparent loop mode for LBBD, LB2, LB1 sets non-transparent mode for LBBD, LB2, LB1 '1's are sent on the IOM(R)-2/PCM interface in the corresponding time-slot Data Sheet 224 2001-03-30 PEF 81912/81913 Register Description U/IOM Close LBBD, LB2, LB1 Towards U or Towards IOM(R) - Switch that selects whether loopback LB1, LB2 or LBBD is closed towards U or towards IOM(R)-2 - the setting affects all test loops, LBBD, LB2 and LB1 - an individual selection for LBBD, LB2, LB1 is not possible 0= 1= LBBD LB1, LB2, LBBD loops are closed from IOM(R)-2 to IOM(R)-2 LB1, LB2, LBBD loops are closed from U to U Close Complete Loop (B1, B2, D) Near the System Interface the direction towards the loop is closed is determined by bit `U/IOM' 0= 1= complete loopback open complete loopback closed LB2 Close Loop B2 Near the System Interface the direction towards the loop is closed is determined by bit `U/IOM' 0= 1= loopback B2 open loopback B2 closed LB1 Close Loop B1 Near the System Interface the direction towards the loop is closed is determined by bit `U/IOM' 0= 1= loopback B1 open loopback B1 closed 1) 2) If in state Transparent the DLB-loopback is closed from IOM- to IOM, then C/I-code 'DC' instead of 'AI' is issued on the IOM(R)-2-interface. If in state Transparent the non-transparent LBBD-loopback is closed from U- to U, then C/I-code 'DC' instead of 'AI' is issued on the IOM(R)-2-interface. However, the correct C/I-code 'AI' can be read from register UCIR. 4.11.15 FEBE - Far End Block Error Counter Register The Far End Block Error Counter Register contains the FEBE value. If the register is read out it is automatically reset to `0'. FEBE Reset Value: 7 00H 6 5 4 3 2 1 0 read Address: 71H Data Sheet 225 2001-03-30 PEF 81912/81913 Register Description FEBE Counter Value 4.11.16 NEBE - Near End Block Error Counter Register The Near End Block Error Counter Register contains the NEBE value. If the register is read out it is automatically reset to `0'. NEBE Reset Value: 7 00H 6 5 4 3 2 1 0 read Address: 72H NEBE Counter Value 4.11.17 ISTAU - Interrupt Status Register U-Interface The Interrupt Status register U-interface generates an interrupt for the unmasked interrupt flags. Refer to Chapter 2.4.12 for details on masking and clearing of interrupt flags. For the timing of the interrupt flags ISTAU(3:0) refer to Chapter 2.4.2.4. ISTAU Reset Value: 7 MLT 00H 6 CI 5 FEBE/ NEBE 4 M56 3 M4 2 EOC 1 6ms 0 12ms read Address: 7AH MLT MLT interrupt indication 0= 1= inactive MLT interrupt has occurred CI C/I code indication the CI interrupt is generated independently on OPMODE.UCI 0= 1= inactive CI code change has occurred Data Sheet 226 2001-03-30 PEF 81912/81913 Register Description FEBE/ NEBE Far End/Near End Block Error indication register M56R notifies whether a FEBE or NEBE has been detected 0= 1= M56 inactive FEBE/NEBE occurred Validated new M56 bit data received from U-interface 0= 1= inactive change of any M5, M6 bit has been detected in receive direction M4 Validated new M4 bit data received from U-interface 0= 1= inactive change of any M4 bit has been detected in receive direction EOC Validated new EOC data received from U-interface 0= 1= inactive new EOC message has been received and acknowledged from U 6 ms 6 ms timer for the transmission of EOC commands on U 0= 1= inactive indicates when a EOC command is going to be issued on U 12 ms Superframe marker (each 12 ms) is going to be issued on U in transmit direction Bellcore test requirement: SR-NWT-002397 0= 1= inactive indicates when a SF marker is going to be transmitted on U 4.11.18 MASKU - Mask Register U-Interface The Interrupt Mask register U-Interface selectively masks each interrupt source in the ISTAU register by setting the corresponding bit to `1'. MASKU Reset Value: 7 FFH 6 5 4 3 2 1 0 read*)/write Address: 7BH Data Sheet 227 2001-03-30 PEF 81912/81913 Register Description MASKU Value Bit 0..7 Mask bits 0= 1= interrupt active interrupt masked 4.11.19 FW_VERSION FW_VERSION Register contains the Firmware Version number FW_VERSION Reset value: 6xH 7 6 5 4 3 2 1 0 read Address: 7DH Firmware Version Number Version 1.2 : 6DH Version 1.3 : 6CH Data Sheet 228 2001-03-30 PEF 81912/81913 Electrical Characteristics 5 5.1 * Electrical Characteristics Absolute Maximum Ratings Symbol Limit Values -40 to 85 - 65 to 150 4.2 -0.3 to VDD + 3.3 (max. < 5.5) Unit C C V V Parameter Ambient temperature under bias TA TSTG Storage temperature VDD Maximum Voltage on VDD Maximum Voltage on any pin with respect to VS ground ESD integrity (according EIA/JESD22-A114B (HBM)): 2 kV Note: Stress above those listed here may cause permanent damage to the device. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. Line Overload Protection The Q-SMINT(R)IX is compliant to ESD tests according to ANSI / EOS / ESD-S 5.1-1993 (CDM), EIA/JESD22-A114B (HBM) and to Latch-up tests according to JEDEC EIA / JESD78. From these tests the following max. input currents are derived (Table 41): * Table 41 Test ESD Latch-up DC Maximum Input Currents Pulse Width 100 ns 5 ms -Current 1.3 A +/-200 mA 10 mA Remarks 3 repetitions 2 repetitions, respectively Data Sheet 229 2001-03-30 PEF 81912/81913 Electrical Characteristics 5.2 * DC Characteristics VDD/VDDA = 3.3 V +/- 5% ; VSS/VSSA = 0 V; TA = -40 to 85 C Digital Pins All All except DD/DU ACT,LP2I MCLK DD/DU ACT,LP2I MCLK All Analog Pins AIN, BIN Input leakage current ILI 70 A 0 V VIN VD D Parameter Input low voltage Input high voltage Output low voltage Output high voltage Output low voltage Output high voltage (DD/DU push-pull) Input leakage current Symbol Limit Values min. VIL VIH VOL1 VOH1 VOL2 VOH2 ILI 2.4 10 10 2.4 0.45 -0.3 2.0 max. 0.8 5.25 0.45 Unit V V V V V V A A Test Condition IOL1 = 3.0 mA IOH1 = 3.0 mA IOL2 = 4.0 mA IOH2 = 4.0 mA 0 V VIN VDD 0 V VIN VDD Output leakage current ILO Table 42 Pin SX1,2 S-Transceiver Characteristics Symbol Limit Values min. typ. 2.2 max. 2.31 V VX 2.03 Unit Test Condition RL = 50 Parameter Absolute value of output pulse amplitude (VSX2 - VSX1) S-Transmitter output impedance SX1,2 ZX ZR 10 0 10 100 34 k k see 1) see 2)3) VDD = 3.3 V VDD = 0 V SR1,2 S-Receiver input impedance 1) Requirement ITU-T I.430, chapter 8.5.1.1a): 'At all times except when transmitting a binary zero, the output impedance , in the frequency range of 2kHz to 1 MHz, shall exceed the impedance indicated by the template in Figure 11. The requirement is applicable with an applied sinusoidal voltage of 100 mV (r.m.s value)' Data Sheet 230 2001-03-30 PEF 81912/81913 Electrical Characteristics 2) Requirement ITU-T I.430, chapter 8.5.1.1b): 'When transmitting a binary zero, the output impedance shall be > 20 .': Must be met by external circuitry. Requirement ITU-T I.430, chapter 8.5.1.1b), Note: 'The output impedance limit shall apply for a nominal load impedance (resistive) of 50 . The output impedance for each nominal load shall be defined by determining the peak pulse amplitude for loads equal to the nominal value +/- 10%. The peak amplitude shall be defined as the the amplitude at the midpoint of a pulse. The limitation applies for pulses of both polarities.' 3) Table 43 U-Transceiver Characteristics Limit Values min. typ. max. dB 50 5 55 16 (PEF 81912) 9 (PEF 81913) 80 k %3) mV peak Unit Receive Path Signal / (noise + total harmonic distortion)1) 652) DC-level at AD-output Threshold of level detect (measured between AIN and BIN with respect to zero signal) Input impedance AIN/BIN Transmit Path Signal / (noise + total harmonic distortion)4) 70 Common mode DC-level Offset between AOUT and BOUT Absolute peak voltage for a single +3 or -3 pulse measured between AOUT and BOUT5) Output impedance AOUT/BOUT: Power-up Power-down 1) 2) 3) 4) 45 4 dB 1.65 2.5 1.69 35 2.58 V mV V 1.61 2.42 0.8 3 1.5 6 Test conditions: 1.4 Vpp differential sine wave as input on AIN/BIN with long range (low, critical range). Versions PEF 8x913 with enhanced performance of the U-interface are tested with tightened limit values The percentage of the "1 "-values in the PDM-signal. Interpretation and test conditions: The sum of noise and total harmonic distortion, weighted with a low pass filter 0 to 80 kHz, is at least 70 dB below the signal for an evenly distributed but otherwise random sequence of +3, +1, -1, -3. The signal amplitude measured over a period of 1 min. varies less than 1%. 5) Data Sheet 231 2001-03-30 PEF 81912/81913 Electrical Characteristics 5.3 * Capacitances TA = 25 C, 3.3 V 5 % VSSA = 0 V, VSSD = 0 V, fc = 1 MHz, unmeasured pins grounded. Table 44 Parameter Digital pads: Input Capacitance I/O Capacitance Analog pads: Load Capacitance Pin Capacitances Symbol Limit Values Unit min. CIN CI/O CL max. 7 7 3 pF pF pF pin AIN, BIN Remarks 5.4 * Power Consumption Power Consumption VDD=3.3 V, VSS=0 V, Inputs at VSS/VDD, no LED connected, 50% bin. zeros, no output loads except SX1,2 (50 1)) Parameter Operational U and S enabled, IOM(R)-2 off Limit Values min. typ. 235 200 Power Down 1) Unit Test Condition max. mW mW mW U: ETSI loop 1 (0 m) U: ETSI Loop 2.(typical line) 15 50 (2 x TR) on the S-bus. 5.5 Supply Voltages VDDD = + Vdd 5% VDDA = + Vdd 5% The maximum sinusoidal ripple on VDD is specified in the following figure: Data Sheet 232 2001-03-30 PEF 81912/81913 Electrical Characteristics * mV (peak) 200 100 Supply Voltage Ripple 10 60 80 100 Frequency / kHz ITD04269.vsd Frequency Ripple Figure 83 Maximum Sinusoidal Ripple on Supply Voltage 5.6 AC Characteristics TA = -40 to 85 C, VDD = 3.3 V 5% Inputs are driven to 2.4 V for a logical "1" and to 0.4 V for a logical "0". Timing measurements are made at 2.0 V for a logical "1" and 0.8 V for a logical "0". The AC testing input/output waveforms are shown in Figure 84. * 2.4 2.0 2.0 Test Points 0.8 0.45 0.8 Device Under Test CLoad=50 pF ITS00621.vsd Figure 84 Input/Output Waveform for AC Tests Parameter All Output Pins Fall time Rise time Data Sheet 233 Symbol Limit values Min Max 30 30 Unit ns ns 2001-03-30 PEF 81912/81913 Electrical Characteristics 5.6.1 * IOM(R)-2 Interface DCL t4 DU/DD (Input) t6 DU/DD (Output) t8 DU/DD (Output) bit n t18 SDS1,2 IOM-Timing.vsd t5 Data valid t7 first bit last bit bit n+1 Figure 85 * IOM(R)-2 Interface - Bit Synchronization Timing t9 FSC t10 DCL t2 t1 BCL t3 t11 t14 t13 t12 Figure 86 Data Sheet IOM(R)-2 Interface - Frame Synchronization Timing 234 2001-03-30 PEF 81912/81913 Electrical Characteristics * Parameter IOM(R)-2 Interface DCL period DCL high DCL low Input data setup Input data hold Symbol Limit values Min t1 t2 t3 t4 t5 565 200 200 20 20 100 Typ 651 310 310 Max 735 420 420 Unit ns ns ns ns ns ns Output data from high impedance to t6 active (FSC high or other than first timeslot) Output data from active to high impedance Output data delay from clock FSC high t7 t8 t9 50% of FSC cycle time 65 565 565 1130 65 130 651 651 1302 130 100 80 ns ns ns FSC advance to DCL BCL high BCL low BCL period FSC advance to BCL DCL, FSC rise/fall t10 t11 t12 t13 t14 t15 195 735 735 1470 195 30 200 150 120 ns ns ns ns ns ns ns ns ns Data out fall (CL = 50 pF, R = 2 k to t16 VDD, open drain) Data out rise/fall (CL = 50 pF, tristate) Strobe Signal Delay t17 t18 Note: At the start and end of a reset period, a frame jump may occur. This results in a DCL, BCL and FSC high time of min. 130 ns after this specific event. Data Sheet 235 2001-03-30 PEF 81912/81913 Electrical Characteristics 5.6.2 * Serial P Interface t1 t4 CS t11 SCLK t6 SDR t8 SDX t10 SCI_timing.vsd t5 t3 t2 t7 t9 Figure 87 * Serial Control Interface Symbol Limit values Min Max ns ns ns ns ns ns ns 60 40 60 10 ns ns ns ns 200 80 80 20 10 15 15 Unit Parameter SCI Interface SCLK cycle time SCLK high time SCLK low time CS setup time CS hold time SDR setup time SDR hold time SDX data out delay CS high to SDX tristate SCLK to SDX active CS high to SCLK t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 Data Sheet 236 2001-03-30 PEF 81912/81913 Electrical Characteristics 5.6.3 Parallel P Interface Siemens/Intel Bus Mode * tRR RD x CS tRD AD0 - AD7 tDF tDH tRI Data Itt00712.vsd Figure 88 * Microprocessor Read Cycle tWW tWI WR x CS tDW AD0 - AD7 tWD Data Itt00713.vsd Figure 89 * Microprocessor Write Cycle tAA tAD ALE WR x CS or RD x CS tAL AD0 - AD7 tALS tLA Address Itt00714.vsd Figure 90 Multiplexed Address Timing Data Sheet 237 2001-03-30 PEF 81912/81913 Electrical Characteristics * WR x CS or RD x CS tAS A0 - A6 tAH Address Itt009661.vsd Figure 91 Non-Multiplexed Address Timing Motorola Bus Mode * R/W tDSD CS x DS tRD D0 - D7 tRR tRWD tRI tDF tDH Data Itt00716.vsd Figure 92 * Microprocessor Read Timing R/W tDSD CS x DS tDW D0 - D7 tWW tRWD tWI tWD Data Itt09679.vsd Figure 93 Microprocessor Write Cycle Data Sheet 238 2001-03-30 PEF 81912/81913 Electrical Characteristics * CS x DS tAS A0 - A6 tAH Address Itt09662.vsd Figure 94 Non-Multiplexed Address Timing Microprocessor Interface Timing * Parameter ALE pulse width Address setup time to ALE Address hold time from ALE Address latch setup time to WR, RD Address setup time Address hold time ALE guard time DS delay after R/W setup RD pulse width Data output delay from RD Data hold from RD Data float from RD RD control interval1) W pulse width Data setup time to W x CS Data hold time W x CS W control interval R/W hold from CS x DS inactive Symbol tAA tAL tLA tALS tAS tAH tAD tDSD tRR tRD tDH tDF tRI tWW tDW tWD tWI tRWD Limit Values min. 20 10 10 10 10 10 10 10 80 80 0 25 70 60 10 10 70 10 max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Data Sheet 239 2001-03-30 PEF 81912/81913 Electrical Characteristics 1) control interval: tRI' is minimal 70ns for all registers except ISTAU, FEBE and NEBE. However, the time between two consecutive read accesses to one of the registers ISTAU, FEBE or NEBE, respectively, must be longer than 330ns. This does not limit tRI of read sequences, which involve intermediate read access to other registers, as for instance: ISTAU -(tRI)- ISTA -(tRI)- ISTAH -(tRI)- ISTAU. 5.6.4 Table 45 Parameter Reset Reset Input Signal Characteristics Symbol tRST Limit Values min. typ. max. ms Power On the 4 ms are assumed to be long enough for the oscillator to run correctly After Power On 4 Unit Test Conditions Length of active low state 2x DCL clock cycles + 400 ns Delay time for C tC access after RST rising edge * 500 ns tC RST tRST ITD09823.vsd Figure 95 Reset Input Signal Data Sheet 240 2001-03-30 PEF 81912/81913 Electrical Characteristics 5.6.5 * Undervoltage Detection Characteristics VDD VDET VHYS VDDmin t RSTO tACT tACT tDEACT tDEACT t VDDDET.VSD Figure 96 Table 46 Undervoltage Control Timing Parameters of the UVD/POR Circuit VDD= 3.3 V 5 %; VSS= 0 V; TA = -40 to 85 C Parameter Detection Threshold1) Hysteresis Max. rising/falling VDD edge for activation/ deactivation of UVD Max. rising VDD for power-on2) Min. operating voltage VDDmin 1.5 Symbol min. VDET VHys dVDD/dt 2.7 30 Limit Values typ. 2.8 max. 2.92 90 0.1 V mV V/s VDD = 3.3 V 5 % Unit Test Condition 0.1 V/ ms V Data Sheet 241 2001-03-30 PEF 81912/81913 Electrical Characteristics VDD= 3.3 V 5 %; VSS= 0 V; TA = -40 to 85 C Parameter Delay for activation of RSTO Delay for deactivation of RSTO 1) Symbol min. tACT tDEACT Limit Values typ. max. 10 64 Unit Test Condition s ms The Detection Threshold VDET is far below the specified supply voltage range of analog and digital parts of the (R) Q-SMINT IX. Therefore, the board designer must take into account that a range of voltages is existing, where (R) neither performance and functionality of the Q-SMINT IX are guaranteed, nor a reset is generated. If the integrated Power-On Reset of the Q-SMINTIX is selected (VDDDET = '0') and the supply voltage VDD is ramped up from 0V to 3.3V +/- 5%, then the Q-SMINTIX is kept in reset during VDDmin < VDD < VDET + VHys. VDD must be ramped up so slowly that the Q-SMINTIX leaves the reset state after the oscillator circuit has already finished start-up. The start-up time of the oscillator circuit is typically in the range between 3ms and 12ms. 2) Data Sheet 242 2001-03-30 PEF 81912/81913 Package Outlines 6 * Package Outlines Plastic Package, P-MQFP-64 (Metric Quad Flat Package) Data Sheet 243 2001-03-30 PEF 81912/81913 Package Outlines * Plastic Package, P-TQFP-64 (Thin Quad Flat Package) Data Sheet 244 2001-03-30 PEF 81912/81913 Appendix: Differences between Q- and T-SMINTIX 7 Appendix: Differences between Q- and T-SMINT(R)IX The Q- and T-SMINT(R)IX have been designed to be as compatible as possible. However, some differences between them are unavoidable due to the different line codes 2B1Q and 4B3T used for data transmission on the Uk0 line. Especially the pin compatibility between Q- and T-SMINT(R)IX allows for one single PCB design for both series with only some mounting differences. The C software can distinguish between the Q- and T-series by reading the identification register via the IOM(R)-2 (MONITOR channel identification command) or the C interface (register ID.DESIGN), respectively. The following chapter summarizes the main differences between the Q- and TSMINT(R)IX. 7.1 * Pinning Pin Definitions and Functions Pin T/MQFP-64 16 55 41 Q-SMINT(R)IX: 2B1Q Metallic Termination Input (MTI) Power Status (primary) (PS1) Power Status (secondary) (PS2) T-SMINT(R)IX: 4B3T Tie to `1` Tie to `1` Tie to `1` Table 47 Data Sheet 245 2001-03-30 PEF 81912/81913 Appendix: Differences between Q- and T-SMINTIX 7.2 7.2.1 * U-Transceiver U-Interface Conformity Related Documents to the U-Interface Q-SMINT(R)IX: 2B1Q T-SMINT(R)IX: 4B3T conform to annex B conform to annex A compliant to 10 ms interruptions Table 48 ETSI: TS 102 080 ANSI: T1.601-1998 (Revision of ANSI T1.6011992) CNET: ST/LAA/ELR/DNP/ 822 RC7355E FTZ-Richtlinie 1 TR 220 conform not required MLT input and decode logic conform conform not required not required not required conform Data Sheet 246 2001-03-30 PEF 81912/81913 Appendix: Differences between Q- and T-SMINTIX 7.2.2 * U-Transceiver State Machines T14S SN0 . T14E T14S TL Pending Timing DC Any State SSP or C/I= 'SSP' T14S DI . SN0 Deactivated DC TIM DI AR or TL SP Test DR . . SN0 IOM Awaked PU AR or TL SN0 Reset Any State Pin-RST or C/I= 'RES' DR ARL . DI DI & NT-AUTO T1S, T11S TN DC . Alerting PU T12S T1S T11S . TN Alerting 1 DR T11E T12S T1S, T11S T11E T12S SN1 . EC-Training AL DC LSEC or T12E LSUE or T1E . SN1 EC-Training DC SN0 SN1 DI . EC-Training 1 DR LSEC or T12E act=0 SN3 Wait for SF AL DC BBD1 & SFD .. BBD0 & FD EQ-Training DC T20S SN3T act=0 Analog Loop Back AR LSUE or T1E SN2 . T20E & BBD0 & SFD LOF Wait for SF DC DI SN3/SN3T act=1/0 Pend.Deact. S/T DR LSUE 1) 3) dea=0 LOF SN3/SN3T act=0 Synchronized 1 DC uoa=1 1) dea=0 LSUE uoa=0 dea=0 LSUE LOF SN3/SN3T 1) act=0 Synchronized 2 2) AR/ARL Al LOF SN3/SN3T 1) act=1 Wait for Act 2) El1 AR/ARL act=1 act=0 uoa=0 dea=0 LSUE Any State DT or C/I='DT' LOF El1 act=1 SN3T Transparent 2) AI/AIL act=1 & Al uoa=0 dea=0 LSUE Yes SN3/SN3T 1) act=0 Error S/T act=0 2) AR/ARL dea=0 uoa=0 LSUE uoa=1 ? No dea=1 LOF . SN0 Pend Receive Res. T13S EI1 LSU or ( /LOF & T13E ) T7S LOF SN3/SN3T act=1/0 3) Pend.Deact. U DC LSU 1) T7E & DI . SN0 Receive Reset DR T7S TL Figure 97 INTC-Q Compatible State Machine Q-SMINT(R)IX: 2B1Q Data Sheet 247 2001-03-30 PEF 81912/81913 Appendix: Differences between Q- and T-SMINTIX * T14S SN0 . T14E T14S TL Pending Timing DC Any State SSP or C/I= 'SSP' T14S DI . SN0 Deactivated DC TIM DI AR or TL SP Test DR . TIM . SN0 IOM Awaked PU AR or TL SN0 Reset Any State Pin-RST or C/I= 'RES' DR ARL . DI T1S, T11S TN Alerting PU T11E . T1S T11S . TN Alerting 1 DR T11E T12S T1S, T11S T12S SN1 . EC-Training AL DR LSEC or T12E LSUE or T1E . SN1 EC-Training PU SN0 T12S SN1 DI or TIM . EC-Training 1 DR LSEC or T12E act=0 SN3 Wait for SF AL DR BBD1 & SFD .. BBD0 & FD LOF EQ-Training PU T20S SN3T act=0 Analog Loop Back AR LSUE or T1E . SN2 Wait for SF PU T20E & BBD0 & SFD SN3/SN3T 1) act=1/0 Pend.Deact. S/T DR LSUE 3) DI or TIM dea=0 LSUE uoa=0 dea=0 LSUE dea=0 LOF SN3/SN3T 1) act=0 Synchronized 1 PU uoa=1 LOF SN3/SN3T act=0 Synchronized 2 2) AR/ARL Al 1) LOF El1 SN3/SN3T 1) act=1 Wait for Act 2) AR/ARL act=1 act=0 uoa=0 dea=0 LSUE Any State DT or C/I='DT' LOF El1 act=1 SN3T Transparent 2) AI/AIL act=1 & Al uoa=0 dea=0 LSUE Yes SN3/SN3T 1) act=0 Error S/T act=0 2) AR/ARL dea=0 uoa=0 LSUE uoa=1 ? No dea=1 . SN0 Pend Receive Res. T13S DR LSU or ( /LOF & T13E ) T7E & TIM T7E & DI T7S LOF SN3/SN3T act=1/03) LOF Pend.Deact. U DR LSU 1) . SN0 Receive Reset DR T7S TL Figure 98 Data Sheet Simplified State Machine Q-SMINT(R)IX: 2B1Q 248 2001-03-30 PEF 81912/81913 Appendix: Differences between Q- and T-SMINTIX * AWR U0 IOM Awaked DC AR T6S U1W Start Awaking Uk0 RSY T6S T6E U0 Awake Signal Sent RSY AWR T13S T13E U0 Ack. Sent / Received RSY AWT AWR (DI & T05E) T12S U1A Synchronizing RSY U2 (U0 & T12E) T05S U0 Pend. Deactivation DR T05S DT U1 SBC Synchronizing AR / ARL AI DI U3 Wait for Info U4H AR / ARL U4H U0 U5 Transparent AI / AIL U0 LOF U0 Loss of Framing RSY U0 LOF U0 LOF DI T13S U1W Sending Awake-Ack. RSY T13S AWT T6S T05S T05S T05E U0 Deactivating DC AWR TIM AR U0 Deactivated DC U0, DA AWR DI SP / U0 Test DR SSP ANY STATE RES U0 Reset DR NT_SM_4B3T_cust.emf Figure 99 IEC-T/NTC-T Compatible State Machine T-SMINT(R)IX: 4B3T Both the Q- and the T-SMINT(R)IX U-transceiver can be controlled via state machines, which are compatible to those defined for the old NT generation INTC-Q and NTC-T. Additionally, the Q-SMINT(R)IX possesses a newly defined, so called `simplified` state machine. This simplified state machine can be used optionally instead of the INTC-Q compatible state machine and eases the U-transceiver control by software. Such a simplified state machine is not available for the T-SMINT(R)IX. Data Sheet 249 2001-03-30 PEF 81912/81913 Appendix: Differences between Q- and T-SMINTIX 7.2.3 Table 49 Code Command/Indication Codes C/I Codes Q-SMINT(R)IX: 2B1Q IN OUT DR - - - EI1 - - PU AR - ARL - AI - AIL DC T-SMINT(R)IX: 4B3T IN TIM - - - - SSP DT - AR - - - AI RES - DI OUT DR - - - RSY - - - AR - ARL - AI - AIL DC 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 TIM RES - - EI1 SSP DT - AR - ARL - AI - - DI Data Sheet 250 2001-03-30 PEF 81912/81913 Appendix: Differences between Q- and T-SMINTIX 7.2.4 * Interrupt Structure M56R 7 0 MS2 MS1 NEBE M61 M52 M51 0 FEBE + OPMODE.MLT CRC, TLL, no Filtering MFILT + M4R 7 AIB UOA M46 M45 M44 SCO DEA 0 ACT MFILT M4RMASK 7 UCIR CRC, TLL, no Filtering C/I C/I C/I 0 C/I EOCR 15 MFILT 11 a1 a2 TLL, CHG, no Filtering ISTAU 7 MLT CI FEBE/ NEBE M56 MASKU MLT CI FEBE/ NEBE M56 M4 EOC 6ms 12ms 7 0 i8 M4 EOC 6ms 0 12ms ISTA U Reserved MASK interr_U_Q2.vsd 0 INT Figure 100 Interrupt Structure U-Transceiver Q-SMINT(R)IX: 2B1Q Data Sheet 251 2001-03-30 PEF 81912/81913 Appendix: Differences between Q- and T-SMINTIX * UCIR 7 0 0 0 0 C/I C/I C/I 0 C/I ISTAU 7 0 CI RDS 0 0 0 0 0 1ms MASKU 1 CI RDS 1 1 1 1 1ms ISTA U S ... ... ... ... ... ... MASK intstruct_4b3t.emf INT Figure 101 Interrupt Structure U-Transceiver T-SMINT(R)IX: 4B3T Data Sheet 252 2001-03-30 PEF 81912/81913 Appendix: Differences between Q- and T-SMINTIX 7.2.5 Register Summary U-Transceiver U-Interface Registers Q-SMINT(R)IX: 2B1Q Name OPMODE 7 0 6 UCI 5 FEBE 4 MLT 3 0 2 CI_ SEL 1 0 0 0 ADDR R/W RES 60H 61H 62H a2 i6 a2 i6 a3 i7 a3 i7 d/m i8 d/m i8 63H 64H 65H 66H 67H 68H 69H 6AH FEBE FEBE 6BH 6CH 6DH 6EH 40 KHz 6FH LB1 70H 71H 72H 73H79H W R 0F FFH 01H 00H R*/W 00H R*/W A8H R BEH R*/W 14H R*/W 14H MFILT M56 FILTER M4 FILTER reserved EOC FILTER EOCR 0 i1 0 i2 0 i2 0 i3 0 i3 0 i4 0 i4 a1 i5 a1 i5 EOCW 0 i1 M4RMASK M4WMASK M4R M4W M56R M56W UCIR UCIW TEST 0 1 0 0 0 M4 Read Mask Bits M4 Write Mask Bits verified M4 bit data of last received superframe M4 bit data to be send with next superframe MS2 1 0 0 0 MS1 1 0 0 0 NEBE 1 0 0 0 CCRC M61 M61 M52 M52 M51 M51 R*/W BEH R W R W 1FH FFH 00H 01H C/I code output C/I code input +-1 Tones LBBD 0 R*/W 00H R*/W 08H R R 00H 00H LOOP FEBE NEBE 0 DLB TRANS U/IOM(R) 1 LB2 FEBE Counter Value NEBE Counter Value reserved Data Sheet 253 2001-03-30 PEF 81912/81913 Appendix: Differences between Q- and T-SMINTIX Name ISTAU 7 MLT 6 CI 5 FEBE/ NEBE FEBE/ NEBE 4 M56 3 M4 2 EOC 1 6ms 0 12ms ADDR R/W RES 7AH 7BH 7CH 7DH 7EH7FH R 6xH R 00H MASKU MLT CI M56 M4 EOC 6ms 12ms R*/W FFH reserved FW_ VERSION FW Version Number reserved Data Sheet 254 2001-03-30 PEF 81912/81913 Appendix: Differences between Q- and T-SMINTIX U-Interface Registers T-SMINT(R)IX: 4B3T Name OPMODE 7 0 6 UCI 5 0 4 0 3 0 2 0 1 0 0 0 ADDR R/W RES 60H 61H6CH C/I code output C/I code input 6DH 6EH 6FH LBBD LB2 LB1 70H 71H 72H 73H79H 0 1 0 1 1 ms 1 ms 7AH 7BH 7CH 7DH 7EH7FH R 3xH R 00H R 00H R*/W 08H R W 00H 01H R*/W 00H reserved UCIR UCIW 0 0 0 0 0 0 0 0 reserved LOOP 0 DLB TRANSU/IOM(R) 1 reserved RDS Block Error Counter Value reserved ISTAU MASKU 0 1 CI CI RDS RDS 0 1 0 1 R*/W FFH reserved FW_ VERSION FW Version Number reserved Data Sheet 255 2001-03-30 PEF 81912/81913 Appendix: Differences between Q- and T-SMINTIX 7.3 External Circuitry The external circuitry of the Q- and T-SMINT(R)IX is equivalent; however, some external components of the U-transceiver hybrid must be dimensioned different for 2B1Q and 4B3T. All information on the external circuitry is preliminary and may be changed in future documents. * AOUT R3 RT n BIN R4 RCOMP RPTC C AIN >1 Loop R4 RCOMP RPTC R3 extcirc_U_Q2_exthybrid.emf BOUT RT Figure 102 External Circuitry Q- and T-SMINT(R)IX Note: the necessary protection circuitry is not displayed in Figure 102 . Data Sheet 256 2001-03-30 PEF 81912/81913 Appendix: Differences between Q- and T-SMINTIX Table 50 Component Transformer: Ratio Main Inductivity Resistance R3 Resistance R4 Resistance RT Capacitor C RPTC and RComp Dimensions of External Components Q-SMINT(R)IX: 2B1Q 1:2 14.5 mH 1.3 k 1.0 k 9.5 27 nF 2RPTC + 8RComp = 40 T-SMINT(R)IX: 4B3T 1:1.6 7.5 mH 1.75 k 1.0 k 25 15 nF n2 x (2RCOMP + RB) + RL = 20 Data Sheet 257 2001-03-30 PEF 81912/81913 Index 8 A Index I Message Transfer Modes 119 Absolute Maximum Ratings 229 Address Space 155 B Block Diagram 7 Block Error Counters 80 C C/I Channel Detailed Registers 168 Functional Description 50 C/I Codes S-Transceiver 108 U-Transceiver 82 Controller Data Access (CDA) 31 Cyclic Redundancy Check 78 Identification via Monitor Channel 48 via Register Access 198 Interrupts 156 IOM(R)-2 Interface AC Characteristics 234 Activation/Deactivation 58 Detailed Registers 199 Frame Structure 28 Functional Description 28 L Layer 1 Activation/Deactivation 139 Loopbacks 144 LED Pins 13 Line Overload Protection 229 D DC Characteristics 230 D-Channel Access Control Functional Description 51 State Machine 55 Differences between Q- and T-SMINT 245 M Maintenance Channel 63 Metallic Loop Termination 98 Microcontroller Clock Generation 24 Microcontroller Interfaces Interface Selection 17 Parallel Microcontroller Interface 22 Serial Control Interface (SCI) 18 Monitor Channel Detailed Registers 211 Error Treatment 46 Functional Description 42 Handshake Procedure 42 Interrupt Logic 49 Time-Out Procedure 49 E EOC 66 External Circuitry S-Transceiver 151 U-Transceiver 149 F Features 3 H HDLC Controller Data Reception 120 Data Transmission 128 Detailed Registers 168 Functional Description 119 O Oscillator Circuitry 153 Overhead Bits 74 P Package Outlines 243 258 2001-03-30 Data Sheet PEF 81912/81913 Index Parallel Microcontroller Interface AC-Characteristics 237 Functional Description 22 Pin Configuration 6 Pin Definitions and Functions 8 Power Consumption 232 Power Supply Blocking 149 Power-On Reset 27, 241 Functional Description 60 State Machine, Simplified NT 94 State Machine, Standard NT 86 W Watchdog Timer 26 R Register Summary 158 Reset Generation 25 Input Signal Characteristics 240 Power-On Reset 27, 241 Under Voltage Detection 27, 241 S S/Q Channels 104 Scrambling/ Descrambling 82 Serial Control Interface (SCI) AC-Characteristics 236 Functional Description 18 Serial Data Strobe Signal 41 Stop/Go Bit Handling 53 S-Transceiver Detailed Registers 186 Functional Description 102 State Machine, LT-S 114 State Machine, NT 110 Supply Voltages 232 Synchronous Transfer 37 System Integration 14 T Test Modes 14 TIC Bus Handling 52 U U-Interface Hybrid 149 Under Voltage Detection 27, 241 U-Transceiver Detailed Registers 214 Data Sheet 259 2001-03-30 Infineon goes for Business Excellence "Business excellence means intelligent approaches and clearly defined processes, which are both constantly under review and ultimately lead to good operating results. Better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction." Dr. Ulrich Schumacher http://www.infineon.com Published by Infineon Technologies AG |
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